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    NON-VOLATILE MEMORY CELL
    51.
    发明申请
    NON-VOLATILE MEMORY CELL 审中-公开
    非挥发性记忆细胞

    公开(公告)号：US20050179095A1

    公开(公告)日：2005-08-18

    申请号：US10908114

    申请日：2005-04-28

    申请人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

    发明人： Ching-Hsiang Hsu ,  Shih-Jye Shen ,  Hsin-Ming Chen ,  Hai-Ming Lee

    IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L29/7923

    摘要： A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between the second doped region and a third doped region from among the three P-type doped regions, and a second gate formed on the second stacked dielectric layer.

    摘要翻译： 公开了一种存储器单元。 存储单元包括N阱，形成在N型阱上的三个P型掺杂区，形成在N型阱上的第一层叠电介质层，以及在三层阱中的第一掺杂区和第二掺杂区之间 P型掺杂区域，形成在第一堆叠介质层上的第一栅极，形成在N型阱上的第二堆叠电介质层，以及在三个P型掺杂区域中的第二掺杂区域和第三掺杂区域之间， 以及形成在所述第二堆叠电介质层上的第二栅极。

    Single poly UV-erasable programmable read only memory
    53.
    发明授权
    Single poly UV-erasable programmable read only memory 有权
    单个聚UV可擦除可编程只读存储器

    公开(公告)号：US06882574B2

    公开(公告)日：2005-04-19

    申请号：US10605235

    申请日：2003-09-17

    申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

    发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0408 ,  G11C16/0433 ,  G11C2216/10 ,  G11C2216/18 ,  H01L27/11521 ,  H01L27/11558

    摘要： An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the first P-type MOS transistor connected to source line voltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the second P-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.

    摘要翻译： 可擦除可编程只读存储器包括两个串联的P型金属氧化物半导体（MOS）晶体管，其中第一P型MOS晶体管用作选择晶体管，第一P型MOS晶体管的栅极耦合到选择栅极 电压，连接到源极线电压的第一P型MOS晶体管的第一节点，与第二P型MOS晶体管的第一节点连接的第一P型MOS晶体管的第二节点，其中， 第二P型MOS晶体管连接到位线电压，其中第二P型MOS晶体管的栅极用作浮置栅极，其中可擦除可编程只读存储器不需要在控制栅极上偏置一定电压， 编程，从而将热载体注入到浮动栅极上，并且其中可擦除可编程只读存储器被对紫外线（UV）光透明的电介质材料封盖。

    Low voltage single-poly flash memory cell and array
    54.
    发明授权
    Low voltage single-poly flash memory cell and array 失效
    低电压单聚光闪存单元和阵列

    公开(公告)号：US06750504B2

    公开(公告)日：2004-06-15

    申请号：US10063444

    申请日：2002-04-24

    申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Wei-Zhe Wong ,  Ching-Hsiang Hsu

    发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Wei-Zhe Wong ,  Ching-Hsiang Hsu

    IPC分类号： H01L2972

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/115

    摘要： A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.

    摘要翻译： 低电压单聚光闪存单元包括第一导电类型的第一离子阱，形成在第一离子阱上的第二导电类型的第二离子阱，电荷存储层，其包含第一绝缘层，俘获层， 以及位于所述第二离子阱上的第二绝缘层，位于所述电荷存储层上的栅极，位于所述电荷存储层的两侧的所述第二导电类型的源极和漏极以及所述第一导电性的离子掺杂区域 形成在所述第二离子阱中并且在所述源的下面和周围以及所述第一绝缘层的底部的至少一部分。

    Nonvolatile semiconductor memory capable of random programming
    55.
    发明授权
    Nonvolatile semiconductor memory capable of random programming 失效
    非易失性半导体存储器，能够进行随机编程

    公开(公告)号：US06504763B1

    公开(公告)日：2003-01-07

    申请号：US09683845

    申请日：2002-02-21

    申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

    发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

    IPC分类号： G11C1604

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the first conductivity type isolated by an STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate used to provide a first predetermined voltage for the shallow ion well during a data program mode via a conductive plug which electrically connects to the bit line and extends downward to the shallow ion well. Consequently, during a programming operation, only a selected word line is required to have an appropriate voltage applied to it. Thus, the power needed is reduced and access time is shortened.

    摘要翻译： 能够进行随机编程的非易失性半导体存储器具有具有存储区域的第一导电类型的半导体衬底，位于存储区域内的半导体衬底中的第二导电类型的深离子阱，第一导电类型的浅离子阱 通过深离子阱内的STI层隔离，位于浅离子阱内的半导体衬底上的至少一个NAND单元块，以及位于半导体衬底上方的位线，用于为浅离子阱提供第一预定电压 通过电连接到位线并向下延伸到浅离子阱的导电插头的数据程序模式。 因此，在编程操作期间，仅需要选择的字线来施加适当的电压。 因此，所需的功率减少，并且访问时间缩短。

    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE
    57.
    发明申请
    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE 审中-公开
    绝缘体绝缘体（SOI）存储器件

    公开(公告)号：US20070296034A1

    公开(公告)日：2007-12-27

    申请号：US11759949

    申请日：2007-06-08

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558

    摘要： A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.

    摘要翻译： 单多晶硅存储单元包括与SOI衬底上的浮栅PMOS晶体管串联连接的PMOS选择晶体管。 PMOS选择晶体管包括选择栅极，P + SUP源极区和P + SUP漏极/源极区。 浮置栅极PMOS晶体管包括浮置栅极，漏极和漏极区域，其中P + 漏极/源极区域由PMOS选择晶体管和浮置栅极PMOS晶体管共享。 漂浮的第一N + +掺杂区域设置在漏极/源极区域内。 与浮动栅极相邻的第一N + H + +掺杂区充当源极接头。

    Fabrication method for non-volatile memory
    59.
    发明授权
    Fabrication method for non-volatile memory 有权
    非易失性存储器的制作方法

    公开(公告)号：US06812083B2

    公开(公告)日：2004-11-02

    申请号：US10463610

    申请日：2003-06-18

    申请人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

    发明人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

    IPC分类号： H01L21336

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C2216/10

    摘要： A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a well. The method further includes biasing the first MOS with a first biasing voltage to actuate the first MOS transistor, biasing the second MOS transistor with a second biasing voltage to enable the second MOS transistor to generate a gate current, and adjusting capacitances between the floating gate of the second MOS transistor and the drain, the source, the control gate, and the well according to voltage difference between the floating gate of the second MOS transistor and the source of the second MOS transistor.

    摘要翻译： 用于非易失性存储器的制造方法包括提供具有控制栅极的第一金属氧化物半导体（MOS）晶体管和具有源极，漏极和浮置栅极的第二MOS晶体管。 第一MOS晶体管和第二MOS晶体管形成在阱上。 该方法还包括以第一偏置电压偏置第一MOS以致动第一MOS晶体管，以第二偏置电压偏置第二MOS晶体管，以使第二MOS晶体管产生栅极电流，并调整第二MOS晶体管的浮置栅极之间的电容 第二MOS晶体管和漏极，源极，控制栅极和阱，根据第二MOS晶体管的浮置栅极和第二MOS晶体管的源极之间的电压差。

    Method for controlling a non-volatile dynamic random access memory
    60.
    发明授权
    Method for controlling a non-volatile dynamic random access memory 有权
    用于控制非易失性动态随机存取存储器的方法

    公开(公告)号：US06829166B2

    公开(公告)日：2004-12-07

    申请号：US10065042

    申请日：2002-09-13

    申请人： Yen-Tai Lin ,  Shih-Jye Shen

    发明人： Yen-Tai Lin ,  Shih-Jye Shen

    IPC分类号： G11C1604

    CPC分类号： G11C14/00

    摘要： A method for controlling a non-volatile dynamic random access memory provides a non-volatile dynamic random access memory having a storage unit and a control unit. The storage unit has a floating gate for storing charges and a control gate for receiving an operating voltage to determine whether a channel is induced on the surface of a substrate. The channel corresponds to a number of charges stored on the floating gate. A parasitic capacitor exists between the storage unit and the control unit, and a capacitance of the parasitic capacitor increases when the channel has been induced. The method includes applying a first predetermined voltage to the control unit and measuring a voltage variance generated by the parasitic capacitor to analyze data stored by the storage unit.

    摘要翻译： 用于控制非易失性动态随机存取存储器的方法提供具有存储单元和控制单元的非易失性动态随机存取存储器。 存储单元具有用于存储电荷的浮动栅极和用于接收工作电压的控制栅极，以确定在衬底的表面上是否感应通道。 信道对应于存储在浮动门上的多个电荷。 在存储单元和控制单元之间存在寄生电容器，并且当感应通道时，寄生电容器的电容增加。 该方法包括向控制单元施加第一预定电压并测量由寄生电容器产生的电压变化，以分析由存储单元存储的数据。