公开(公告)号：US20090021986A1

公开(公告)日：2009-01-22

申请号：US12236999

申请日：2008-09-24

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

摘要： An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.

摘要翻译： 用于非易失性存储器件的操作方法适用于其中设置衬底的非易失性存储器件。 衬底包括沟槽，设置在衬底中的第一导电类型的第一阱区域和设置在第一导电类型的第一阱区域上方的第二导电类型的第二阱区域。 操作方法包括将第一电压施加到控制栅极，将第二电压施加到漏极区域，并将第三电压施加到源极区域。 此外，采用信道F-N隧道效应来对存储器单元进行编程。

公开(公告)号：US20080198669A1

公开(公告)日：2008-08-21

申请号：US12107774

申请日：2008-04-23

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

摘要翻译： 提供非易失性存储器。 提供了具有多个沟槽和多个选择栅极的衬底。 沟槽平行布置并沿第一方向延伸。 每个选择栅极分别设置在两个相邻沟槽之间的衬底上。 多个选择栅极电介质层设置在选择栅极和衬底之间。 多个复合层设置在沟槽的表面上，并且每个复合层具有电荷捕获层。 多个字线在第二方向上平行布置，其中每条字线填充相邻选择栅极之间的沟槽并设置在复合层上。

公开(公告)号：US07397080B2

公开(公告)日：2008-07-08

申请号：US11306093

申请日：2005-12-15

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L51/20

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

摘要翻译： 提供至少包括衬底，存储单元和源极/漏极区域的非易失性存储器。 存储单元设置在基板上，并且至少包括第一存储单元和第二存储单元。 其中，第一存储单元从衬底向上包括浮动栅极和第一控制栅极。 第二存储器单元设置在第一存储器单元的侧壁上，并且包括电荷捕获层和第二控制栅极。 两个源极/漏极区域设置在存储单元两侧的衬底中。

公开(公告)号：US07391078B2

公开(公告)日：2008-06-24

申请号：US11161398

申请日：2005-08-02

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/62 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.

摘要翻译： 提供非易失性存储器。 提供具有多个沟槽和多个选择栅极的衬底。 沟槽平行布置并沿第一方向延伸。 每个选择栅极分别设置在两个相邻沟槽之间的衬底上。 在选择栅极和衬底之间设置多个选择栅极电介质层。 多个复合层设置在沟槽的表面上，并且每个复合层具有电荷捕获层。 多个字线在第二方向上平行布置，其中每条字线填充相邻选择栅之间的沟槽并且设置在复合层之上。

公开(公告)号：US20070263448A1

公开(公告)日：2007-11-15

申请号：US11778657

申请日：2007-07-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

公开(公告)号：US07291882B2

公开(公告)日：2007-11-06

申请号：US11162893

申请日：2005-09-27

申请人： Ching-Sung Yang ,  Wei-Zhe Wong

发明人： Ching-Sung Yang ,  Wei-Zhe Wong

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type memory transistor includes a first P-type doped region, a second P-type doped region, a second charge storage layer and a second control gate. A common bit line doped region is formed between the N-type memory transistor and the P type memory transistor and electrically connects the first N-type region to the second P-type doped region. A word line electrically connects the first control gate to the second control gate.

摘要翻译： 提供可编程和可擦除的数字开关装置。 在衬底上形成N型存储晶体管和P型存储晶体管。 N型存储晶体管包括第一N型掺杂区，第二N型掺杂区，第一电荷存储层和第一控制栅极。 P型存储晶体管包括第一P型掺杂区，第二P型掺杂区，第二电荷存储层和第二控制栅极。 在N型存储晶体管和P型存储晶体管之间形成公共位线掺杂区域，并将第一N型区域电连接到第二P型掺杂区域。 字线将第一控制栅极电连接到第二控制栅极。

公开(公告)号：US20060039200A1

公开(公告)日：2006-02-23

申请号：US10907031

申请日：2005-03-17

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： G11C7/10

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568

摘要： A non-volatile memory including a plurality of memory units is provided. Each of the memory units includes a first memory cell and a second memory cell. The first memory cell is disposed over the substrate. The second memory cell is disposed next to the sidewall of the first memory cell and over the substrate. The first memory cell includes a first gate disposed over the substrate, a first composite dielectric layer disposed between the first gate and the substrate. The second memory cell includes a second gate disposed over the substrate and a second composite dielectric layer disposed between the second gate and the substrate and between the second gate and the first memory cell. Each of the first and second composite dielectric layers includes a bottom dielectric layer, a charge-trapping layer and a top dielectric layer.

摘要翻译： 提供包括多个存储单元的非易失性存储器。 每个存储单元包括第一存储单元和第二存储单元。 第一存储单元设置在衬底上。 第二存储单元设置在第一存储单元的侧壁旁边且在衬底上。 第一存储单元包括设置在衬底上的第一栅极，设置在第一栅极和衬底之间的第一复合介电层。 第二存储单元包括设置在衬底上的第二栅极和设置在第二栅极和衬底之间以及第二栅极和第一存储单元之间的第二复合电介质层。 第一和第二复合电介质层中的每一个包括底部电介质层，电荷俘获层和顶部电介质层。

公开(公告)号：US06898126B1

公开(公告)日：2005-05-24

申请号：US10707440

申请日：2003-12-15

申请人： Ching-Sung Yang ,  Hsiang-Chung Chang ,  Wei-Zhe Wong

发明人： Ching-Sung Yang ,  Hsiang-Chung Chang ,  Wei-Zhe Wong

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C5/145 ,  G11C16/10

摘要： A method of programming a flash memory through boosting a voltage level of a source line. The flash memory has n memory cell transistors cascaded in series, a local bit line positioned above the n memory cell transistors, a buried bit line positioned under the n memory cell transistors, and a source line positioned under the buried bit line. The method includes inputting a word line voltage to a control gate of a kth memory cell transistor, and after floating the local bit line, inputting a source line voltage to the source line for inducing an FN tunneling effect inside the kth memory cell transistor through capacitance coupling between the buried bit line and the source line.

摘要翻译： 一种通过提高源极线的电压来编程闪速存储器的方法。 闪速存储器具有串联级联的n个存储单元晶体管，位于n个存储单元晶体管上方的局部位线，位于n个存储单元晶体管下方的掩埋位线以及位于掩埋位线下方的源极线。 该方法包括：将字线电压输入到存储单元晶体管的控制栅极，并且在浮置局部位线之后，向源极线输入源极线电压以引起内部的FN隧道效应 存储单元晶体管，通过掩埋位线和源极线之间的电容耦合。

公开(公告)号：US20080151645A1

公开(公告)日：2008-06-26

申请号：US12043146

申请日：2008-03-06

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： G11C16/06

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

摘要翻译： 提供至少包括衬底，存储单元和源极/漏极区域的非易失性存储器。 存储单元设置在基板上，并且至少包括第一存储单元和第二存储单元。 其中，第一存储单元从衬底向上包括浮动栅极和第一控制栅极。 第二存储器单元设置在第一存储器单元的侧壁上，并且包括电荷捕获层和第二控制栅极。 两个源极/漏极区域设置在存储单元两侧的衬底中。

公开(公告)号：US07235839B2

公开(公告)日：2007-06-26

申请号：US10904749

申请日：2004-11-25

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。