Abstract:
Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.
Abstract:
A single-face clipless pedal structure includes a pedal body for a cleat to be disposed thereon. The axle portion of the pedal body is formed with a recessed stepped portion at the front end thereof The stepped portion is enclosed by a bottom wall and a lateral wall including a stopping face, a first and a second guiding faces at two ends of the stopping face. The first and the second guiding faces are arc concave-shaped. The cleat is formed with an abutting piece downward having an abutting face, a third and a fourth guiding faces at two ends of the abutting face. The abutting face abuts against the stopping face to prohibit the cleat from moving rearward and upward. The third and the fourth guiding faces correspond to the first and the second guiding faces respectively to facilitate the cleat to detach laterally.
Abstract:
An adjusted pedal is provided, including: a pedal body, having two clamp portions respectively configured to engage with a shoe; a pedal shaft, defining an axial direction; an engaging portion, disposed on the pedal body and movably engaged with the pedal shaft so that the pedal body is slidable positionly to the pedal shaft along the axial direction; wherein when the engaging portion is disengaged with the pedal shaft, the pedal body is slidable to the pedal shaft along the axial direction.
Abstract:
A multipurpose pedal includes a spindle assembly and a pedal pivotally assembled with the spindle assembly. The spindle assembly includes a spindle adapting to assemble with a bicycle crank and a tube sleeved on the spindle. The pedal includes a first frame and a second frame mounted in the first frame. Multiple stubs are mounted between the first frame and the second frame. The multiple stubs are replaceable for providing multipurpose.
Abstract:
A quick release device for a pedal includes a spindle, a connecting unit connected to the spindle, and a quick release mechanism connected to the connecting unit. The spindle has a protrusion extending from one end thereof and an annular groove defined in an outer peripheral thereof. The connecting unit has a receiving hole defined therein, a guiding hole defined in a lateral thereof and communicated with the receiving hole, and a retaining hole defined therein and communicated with the receiving hole. The quick release mechanism includes a rod partially received in the guiding hole and a spring biased against the rod toward the receiving hole. In assembly the protrusion engages with the retaining hole and the rod engages with the annular groove.
Abstract:
A bicycle pedal assembly includes a pedal body having a sleeve tube and front and rear protruding portions. A front clamping member is mounted rotatably on the front protruding portion, and is biased by a front biasing member to rotate toward the sleeve tube. A locking member is connected to the front protruding portion, and is operable to abut against the front clamping member so as to lock the latter against rotational movement. A rear clamping member is mounted rotatably on the rear protruding portion, and is biased by a rear biasing member to rotate toward the sleeve tube. An adjusting member is connected to the rear clamping member, and is operable to adjust the biasing force of the rear biasing member.
Abstract:
A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.
Abstract:
A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.