公开(公告)号：US20090109785A1

公开(公告)日：2009-04-30

申请号：US11931098

申请日：2007-10-31

申请人： Theodore W. Houston ,  Andrew Marshall

发明人： Theodore W. Houston ,  Andrew Marshall

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C8/08 ,  G11C11/413

摘要： An integrated circuit (IC) includes at least one memory array having a plurality of memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. A voltage differential generating circuit is operable to provide a differential wordline voltage (VWL) relative to an array supply voltage, wherein the differential is a function of the array supply voltage.

摘要翻译： 集成电路（IC）包括至少一个存储器阵列，其具有以多个行和列排列的多个存储器单元，该阵列还具有用于访问单元行的多个字线和用于访问列的列的多个位线 细胞。 电压差分发生电路可操作以提供相对于阵列电源电压的差分字线电压（VWL），其中差分是阵列电源电压的函数。

公开(公告)号：US07397085B2

公开(公告)日：2008-07-08

申请号：US10007332

申请日：2001-11-08

申请人： Andrew Marshall

发明人： Andrew Marshall

IPC分类号： H01L27/12

CPC分类号： H01L27/0211 ,  H01L27/11 ,  H01L27/1203

摘要： Performance matching devices in SOI are improved by thermally isolating matched devices within a continuous body of active material. Matched devices are isolated by an insulating wall of silicon dioxide (which surrounds the devices) and the oxide layer beneath, and are arranged to minimize effects from external thermal sources.

摘要翻译： 通过在活性材料的连续体内热隔离匹配的器件来改善SOI中的性能匹配器件。 匹配的器件通过二氧化硅（其围绕器件）的绝缘壁和下面的氧化物层隔离，并且被布置成最小化来自外部热源的影响。

公开(公告)号：US20080100369A1

公开(公告)日：2008-05-01

申请号：US11553903

申请日：2006-10-27

申请人： Andrew Marshall ,  Theodore W. Houston

发明人： Andrew Marshall ,  Theodore W. Houston

IPC分类号： H03K3/01

CPC分类号： H03K19/0016 ,  H03K17/687 ,  H03K2217/0018 ,  H03K2217/0036

摘要： The present invention provides an integrated virtual voltage circuit for use with a sub-circuit. In one embodiment, the integrated virtual voltage circuit includes a MOS transistor switch coupled to a supply voltage and configured to employ a drain to provide an operating voltage for the sub-circuit during switch activation. Additionally, the integrated virtual voltage circuit also includes a connection unit coupled to the MOS transistor switch and configured to provide a standby voltage for the sub-circuit during deactivation of the MOS transistor switch wherein the standby voltage is based on a static coupling of the drain to a body region of the MOS transistor switch. In an alternative embodiment, the connection unit is further configured to connect a voltage reference between the supply voltage and the drain of the MOS transistor switch to determine the standby voltage.

摘要翻译： 本发明提供了一种与子电路一起使用的集成虚拟电压电路。 在一个实施例中，集成虚拟电压电路包括耦合到电源电压的MOS晶体管开关，并且被配置为在开关激活期间采用漏极来为子电路提供工作电压。 另外，集成虚拟电压电路还包括耦合到MOS晶体管开关并被配置为在MOS晶体管开关的停用期间为子电路提供备用电压的连接单元，其中待机电压基于漏极的静态耦合 到MOS晶体管开关的体区。 在替代实施例中，连接单元还被配置为连接MOS晶体管开关的电源电压和漏极之间的电压参考以确定待机电压。

公开(公告)号：US20070068915A1

公开(公告)日：2007-03-29

申请号：US11234910

申请日：2005-09-26

申请人： Theodore Houston ,  Andrew Marshall

发明人： Theodore Houston ,  Andrew Marshall

IPC分类号： H05B3/00 ,  H05B1/00 ,  H05B11/00

CPC分类号： G05F3/205 ,  G05F3/30

摘要： The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

摘要翻译： 本发明提供一种与集成电路一起使用的恒温偏压控制器。 在一个实施例中，恒温偏置控制器包括配置成确定集成电路的工作温度的温度感测单元。 此外，恒温偏压控制器还包括电压控制单元，其耦合到温度感测单元并且被配置为基于降低集成电路的静态电流来提供对应于工作温度的反偏压。

公开(公告)号：US20060263913A1

公开(公告)日：2006-11-23

申请号：US11134172

申请日：2005-05-20

申请人： Andrew Marshall

发明人： Andrew Marshall

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L23/34 ,  G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods are provided for maintaining performance of an integrated circuit at a reduced power. The systems and methods employ a performance monitor that generates a signal indicative of at least one performance characteristic of at least a portion of a critical path associated with the integrated circuit. The system further comprises a supply control that adjusts a supply voltage of the integrated circuit to maintain performance at a reduced power based on the signal. A temperature adjustment component can be provided to adjust the signal to compensate for temperature offsets associated with performance of the performance monitor relative to performance of the critical path over different operating temperatures. A performance measurement of the performance monitor can be determined based on the concurrent triggering of the performance monitor and the critical path.

摘要翻译： 提供了用于以降低的功率来维持集成电路的性能的系统和方法。 系统和方法采用性能监视器，其产生指示与集成电路相关联的关键路径的至少一部分的至少一个性能特征的信号。 该系统还包括供电控制，该供应控制器调整集成电路的电源电压，以基于该信号将功率维持在降低的功率。 可以提供温度调节组件来调整信号以补偿与不同工作温度下的关键路径的性能相关的性能监视器性能相关的温度偏移。 可以基于性能监视器和关键路径的并发触发来确定性能监视器的性能测量。

公开(公告)号：US20060173840A1

公开(公告)日：2006-08-03

申请号：US11045248

申请日：2005-01-28

申请人： Hilal Shaath ,  Reena Agarwal ,  Andrew Marshall

发明人： Hilal Shaath ,  Reena Agarwal ,  Andrew Marshall

IPC分类号： G06F17/00

CPC分类号： G06F9/454 ,  Y10S707/99936

摘要： A novel technique for translating a string displayable on a user interface element in a graphical user interface provides a reliable translation without the use of a dictionary. In an embodiment of the invention, an identification is obtained, wherein the identification identifies the user interface element on which the string is displayed. A list is accessed, comprising the identification and a string in the second language. The list is searched to find the identification for the user interface element. Finally, a string is ascertained in the second language corresponding with the found identification in the list. In another embodiment, a string displayable on a user interface element is translated when the location of a user interface selection device on a display is at a location shared by the user interface element.

公开(公告)号：US07085977B2

公开(公告)日：2006-08-01

申请号：US10011220

申请日：2001-10-25

申请人： Andrew Marshall ,  C. Keith Burgess ,  Charles D. Weinberger ,  Madhu Sayala

发明人： Andrew Marshall ,  C. Keith Burgess ,  Charles D. Weinberger ,  Madhu Sayala

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2884

摘要： In one aspect of the invention, a semiconductor die includes a plurality of resistive elements operable to receive a voltage differential between at least two of the resistive elements. The semiconductor die also includes a test circuit coupled to at least three tap points along the resistive elements. The test circuit is operable to measure a voltage at at least two of the tap points. A difference in the voltages between the at least two tap points is proportional to a resistance of the one or more resistive elements between the at least two tap points.

公开(公告)号：US20060082224A1

公开(公告)日：2006-04-20

申请号：US10964802

申请日：2004-10-13

申请人： Andrew Marshall ,  Karan Bhatia

发明人： Andrew Marshall ,  Karan Bhatia

IPC分类号： H02J7/00

CPC分类号： H01L27/101 ,  G01R31/275 ,  Y10T307/826

摘要： A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a plurality of circuit elements (322, 326, 330), and a plurality of transistors (320, 324, 328). Each transistor has a control terminal (314, 316, 318) and a current path coupled between the output terminal and a respective circuit element of the plurality of circuit elements. A control circuit (300) has a plurality of output terminals (314, 316, 318). Each output terminal is coupled to the control terminal of a respective transistor of the plurality of transistors. The control circuit produces control signals at respective output terminals to selectively turn off at least one transistor and turn on at least other transistors of the plurality of transistors at a first time.

摘要翻译： 公开了一种降低布局面积，漏电流和提高产量的电容器电路和方法。 电路包括输出端子（100），多个电路元件（322,326,330）和多个晶体管（320,324,328）。 每个晶体管具有耦合在输出端子和多个电路元件的相应电路元件之间的电流通路的控制端子（314,316,318）。 控制电路（300）具有多个输出端子（314,316,318）。 每个输出端耦合到多个晶体管的相应晶体管的控制端。 控制电路在相应的输出端产生控制信号，以选择性地关断至少一个晶体管，并在第一时间接通多个晶体管的至少其他晶体管。

公开(公告)号：US06982915B2

公开(公告)日：2006-01-03

申请号：US10745429

申请日：2003-12-22

申请人： Theodore W. Houston ,  Luan Dang ,  Andrew Marshall

发明人： Theodore W. Houston ,  Luan Dang ,  Andrew Marshall

IPC分类号： G11C7/04

CPC分类号： G11C11/417

摘要： An electronic device (10), comprising a plurality of data storage cells (12), collectively operable in a data access mode and separately in a sleep mode. The sleep mode comprises a period of time during which the plurality of data cells are not accessed and during which a data state stored in each cell in the plurality of data cells is to be maintained at a valid state. The electronic device further comprises circuitry (18′) for providing at least one temperature-dependent voltage to at least one storage device in each cell in the plurality of data storage cells during the sleep mode.

摘要翻译： 一种包括多个数据存储单元（12）的电子设备（10），它们可以在数据存取模式中共同工作，并且以睡眠模式分开。 休眠模式包括多个数据单元不被访问的时间段，并且多个数据单元中的每个单元中存储的数据状态将被保持在有效状态。 电子设备还包括用于在睡眠模式期间向多个数据存储单元中的每个单元中的至少一个存储设备提供至少一个温度相关电压的电路（18'）。

公开(公告)号：US20050206435A1

公开(公告)日：2005-09-22

申请号：US10803581

申请日：2004-03-17

申请人： Andrew Marshall ,  Wei Dong

发明人： Andrew Marshall ,  Wei Dong

IPC分类号： H03K17/16

CPC分类号： H03K17/163

摘要： The circuit and method for turning on an internal voltage rail includes: coupling a first transistor between a power supply node and an internal voltage rail node; mirroring a current from a second transistor to the first transistor during a turn-on time period; and coupling a control node of the first transistor to a bias voltage node after the turn-on time period. This solution permits current controlled turn-on of the first transistor, but a fully switched-on first transistor once turn-on is complete.

摘要翻译： 用于接通内部电压轨的电路和方法包括：在电源节点和内部电压轨道节点之间耦合第一晶体管; 在导通时间期间将电流从第二晶体管镜像到第一晶体管; 以及在所述导通时间段之后将所述第一晶体管的控制节点耦合到偏置电压节点。 该解决方案允许第一晶体管的电流控制导通，但一旦导通就完成了完全接通的第一晶体管。