Abstract:
Systems and methods for improving the performance of dilution refrigeration systems are described. Filters and traps employed in the helium circuit of a dilution refrigerator may be modified to improve performance. Some traps may be designed to harness cryocondensation as opposed to cryoadsorption. A cryocondensation trap employs a cryocondensation surface having a high thermal conductivity and a high specific heat with a binding energy that preferably matches at least one contaminant but does not match helium. Multiple traps may be coupled in series in the helium circuit, with each trap designed to trap a specific contaminant or set of contaminants. Both cryocondensation and cryoadsorption may be exploited among multiple traps.
Abstract:
Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Abstract:
Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Abstract:
Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
Abstract:
In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
Abstract:
Systems and methods for improving calibration procedures in a quantum processor architecture are described. For example, a dedicated calibration signal source is built into the architecture of the quantum processor for use during calibration. A single calibration signal source is communicatively coupled to many devices in the quantum processor architecture to provide an absolute calibration signal against which various parameters, responses, and/or behaviors of the many devices may be calibrated, either in series or in parallel. The use of a calibration signal source may reduce the time required to calibrate the elements of a quantum processor and/or improve the accuracy/precision of such calibrations.