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51.发明授权System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化公开(公告)号：US07148142B1
公开(公告)日：2006-12-12
申请号：US10874500
申请日：2004-06-23
IPC分类号： H01L21/44
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译： 提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。 该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。 压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。 当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。 卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。 第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。 电介质蚀刻将图案从转印层转移到电介质层中。 然后，金属填充过程用金属填充介电层的双镶嵌开口。
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公开(公告)号：US07105399B1
公开(公告)日：2006-09-12
申请号：US11004951
申请日：2004-12-07
IPC分类号： H01L21/302 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84
摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.
摘要翻译： 通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。 实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。 随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。
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公开(公告)号：US07005386B1
公开(公告)日：2006-02-28
申请号：US10656467
申请日：2003-09-05
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/31058
摘要： According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.
摘要翻译： 根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。 抗反射涂层可以是例如有机材料。 该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。 修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。 根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。
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54.发明申请Method of reducing STI divot formation during semiconductor device fabrication 有权在半导体器件制造期间减少STI纹路形成的方法公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译： 通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。 非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。
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55.发明申请Method of manufacturing a semiconductor device having a U-shaped gate structure 有权制造具有U形门结构的半导体器件的方法公开(公告)号：US20050006666A1
公开(公告)日：2005-01-13
申请号：US10913409
申请日：2004-08-09
申请人： Bin Yu , Shibly Ahmed , Judy An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
发明人： Bin Yu , Shibly Ahmed , Judy An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/786 , H01L31/072
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.
摘要翻译： 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。
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公开(公告)号：US06815268B1
公开(公告)日：2004-11-09
申请号：US10301732
申请日：2002-11-22
IPC分类号： H01L2100
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of forming a gate in a FinFET device includes forming a fin on an insulating layer, forming source/drain regions and forming a gate oxide on the fin. The method also includes depositing a gate material over the insulating layer and the fin, depositing a barrier layer over the gate material and depositing a bottom anti-reflective coating (BARC) layer over the barrier layer. The method further includes forming a gate mask over the BARC layer, etching the BARC layer, where the etching terminates on the barrier layer, and etching the gate material to form the gate.
摘要翻译： 在FinFET器件中形成栅极的方法包括在绝缘层上形成鳍片，形成源极/漏极区域并在鳍片上形成栅极氧化物。 该方法还包括在绝缘层和鳍上沉积栅极材料，在栅极材料上沉积阻挡层并在阻挡层上沉积底部抗反射涂层（BARC）层。 该方法还包括在BARC层上形成栅极掩模，蚀刻BARC层，其中蚀刻在阻挡层上终止，并蚀刻栅极材料以形成栅极。
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57.发明授权公开(公告)号：US06673635B1
公开(公告)日：2004-01-06
申请号：US10185780
申请日：2002-06-28
IPC分类号： H01L2100
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
摘要翻译： 提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。 具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。
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58.发明授权System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合公开(公告)号：US08007631B2
公开(公告)日：2011-08-30
申请号：US11741991
申请日：2007-04-30
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。
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公开(公告)号：US07384569B1
公开(公告)日：2008-06-10
申请号：US10909464
申请日：2004-08-02
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.
摘要翻译： 公开了光刻系统和方法，更具体地说，增强了印迹掩模特征分辨率的系统和方法。 方面产生反馈信息，其通过采用散射测量系统来检测分辨率增强需求，以及通过修剪蚀刻程序减小压印掩模特征尺寸并增加印迹掩模的分辨率，从而有助于控制印迹掩模特征尺寸和分辨率。
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60.发明申请SYSTEM AND METHOD FOR IMPRINT LITHOGRAPHY TO FACILITATE DUAL DAMASCENE INTEGRATION WITH TWO IMPRINT ACTS 有权系统和方法，用于绘制两幅印刷动画的双重增强整合公开(公告)号：US20070283883A1
公开(公告)日：2007-12-13
申请号：US11741991
申请日：2007-04-30
IPC分类号： C23C10/00
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。
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