公开(公告)号：US07579861B2

公开(公告)日：2009-08-25

申请号：US11906365

申请日：2007-10-01

申请人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

发明人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/00384

摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

摘要翻译： 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

公开(公告)号：US20090001468A1

公开(公告)日：2009-01-01

申请号：US12206225

申请日：2008-09-08

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： H01L29/786

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78639

摘要： In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively.

摘要翻译： 在制造包括掩埋绝缘层的晶体管和使用其制造的晶体管的方法中，该方法包括在单晶半导体衬底上顺序地形成牺牲层和顶部半导体层。 在顶部半导体层上形成栅极图案。 形成牺牲隔离物以覆盖栅极图案的侧壁。 在与牺牲间隔物相邻的顶部半导体层的一部分上生长升高的半导体层。 去除牺牲隔离物。 去除牺牲隔离物的顶部半导体层的一部分被蚀刻直到牺牲层被暴露，从而形成将顶部半导体层分离为第一顶部半导体层图案和第二顶部半导体层图案的凹部，其中 分别保持在栅极图案和升高的半导体层之下。 牺牲层被选择性地去除。 形成掩埋绝缘层以填充去除牺牲层的区域。 在凹槽中生长掩埋半导体层。 延伸凹部从凹部延伸并形成为露出半导体衬底。 延伸凹部将掩埋绝缘层分别分别与第一和第二顶部半导体层图案自对准的第一掩埋绝缘层图案和第二掩埋绝缘层图案。

公开(公告)号：US07435657B2

公开(公告)日：2008-10-14

申请号：US11257369

申请日：2005-10-24

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78639

摘要： In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively.

摘要翻译： 在制造包括掩埋绝缘层的晶体管和使用其制造的晶体管的方法中，该方法包括在单晶半导体衬底上顺序地形成牺牲层和顶部半导体层。 在顶部半导体层上形成栅极图案。 形成牺牲隔离物以覆盖栅极图案的侧壁。 在与牺牲间隔物相邻的顶部半导体层的一部分上生长升高的半导体层。 去除牺牲隔离物。 去除牺牲隔离物的顶部半导体层的一部分被蚀刻直到牺牲层被暴露，从而形成将顶部半导体层分离为第一顶部半导体层图案和第二顶部半导体层图案的凹部，其中 分别保持在栅极图案和升高的半导体层之下。 牺牲层被选择性地去除。 形成掩埋绝缘层以填充去除牺牲层的区域。 在凹槽中生长掩埋半导体层。 延伸凹部从凹部延伸并形成为露出半导体衬底。 延伸凹部将掩埋绝缘层分别分别与第一和第二顶部半导体层图案自对准的第一掩埋绝缘层图案和第二掩埋绝缘层图案。

公开(公告)号：US20080157091A1

公开(公告)日：2008-07-03

申请号：US12043587

申请日：2008-03-06

申请人： Dong-Suk Shin ,  Hong-Jae Shin

发明人： Dong-Suk Shin ,  Hong-Jae Shin

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.

摘要翻译： 制造这种器件的导电图案的器件和方法包括形成在单晶半导体衬底上的非单晶半导体图案，形成在非单晶半导体图案的侧壁上的绝缘间隔物，非单晶半导体图案 使用循环选择性外延生长（SEG）工艺选择性地凹陷，以及形成在凹陷的非单晶半导体图案上的硅化物层。

公开(公告)号：US07362375B2

公开(公告)日：2008-04-22

申请号：US10812006

申请日：2004-03-30

申请人： Tae-Sun Kim ,  Dong-Suk Shin ,  Seh-Woong Jeong ,  Kee-Yong Kim ,  Tae-Hee Lee ,  Jae-Hong Park ,  Hyung-Jun Im ,  Kyung-Mook Lim

发明人： Tae-Sun Kim ,  Dong-Suk Shin ,  Seh-Woong Jeong ,  Kee-Yong Kim ,  Tae-Hee Lee ,  Jae-Hong Park ,  Hyung-Jun Im ,  Kyung-Mook Lim

IPC分类号： H04N7/01

CPC分类号： H04N7/012 ,  H04N7/0135 ,  H04N7/0137 ,  H04N7/0142

摘要： In the scanning conversion apparatus, a first converter converts input interlaced scan data into progressive scan data, and a second converter converting the progressive scan data output from the first converter to interlaced scan data.

摘要翻译： 在扫描转换装置中，第一转换器将输入的隔行扫描数据转换为逐行扫描数据，第二转换器将从第一转换器输出的逐行扫描数据转换为隔行扫描数据。

公开(公告)号：US07361563B2

公开(公告)日：2008-04-22

申请号：US11299447

申请日：2005-12-09

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/205 ,  H01L29/80 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

公开(公告)号：US20080079458A1

公开(公告)日：2008-04-03

申请号：US11906365

申请日：2007-10-01

申请人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

发明人： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

IPC分类号： H03K19/0185

CPC分类号： H03K19/00384

摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

摘要翻译： 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

公开(公告)号：US20080073713A1

公开(公告)日：2008-03-27

申请号：US11785994

申请日：2007-04-23

申请人： Ki-Chul Kim ,  Dong-Suk Shin

发明人： Ki-Chul Kim ,  Dong-Suk Shin

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device having a stress enhanced MOS transistor is provided. A MOS transistor may be formed in a desired, or alternatively, a predetermined region of a semiconductor substrate. A first sacrificial pattern, formed over the source and drain regions of a MOS transistor, may expose sidewall spacers and cover the upper region of the gate pattern. Thinner spacers may be formed by etching the exposed sidewall spacers using the first sacrificial pattern as an etch mask. A stress liner may be formed over the MOS transistor having the thinner spacers.

摘要翻译： 提供一种制造具有应力增强型MOS晶体管的半导体器件的方法。 MOS晶体管可以形成在半导体衬底的期望或替代地预定区域中。 形成在MOS晶体管的源极和漏极区域上的第一牺牲图案可以暴露侧壁间隔物并覆盖栅极图案的上部区域。 可以通过使用第一牺牲图案作为蚀刻掩模蚀刻暴露的侧壁间隔物来形成更薄的间隔物。 可以在具有较薄间隔物的MOS晶体管上形成应力衬垫。

公开(公告)号：US07307274B2

公开(公告)日：2007-12-11

申请号：US11204564

申请日：2005-08-15

申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

IPC分类号： H01L29/06

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

公开(公告)号：US20060148154A1

公开(公告)日：2006-07-06

申请号：US11281599

申请日：2005-11-18

申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。