公开(公告)号：US20060038200A1

公开(公告)日：2006-02-23

申请号：US11204564

申请日：2005-08-15

申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

IPC分类号： H01L31/0328 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

公开(公告)号：US07671420B2

公开(公告)日：2010-03-02

申请号：US11281599

申请日：2005-11-18

申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L27/01

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

公开(公告)号：US07307274B2

公开(公告)日：2007-12-11

申请号：US11204564

申请日：2005-08-15

申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

IPC分类号： H01L29/06

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

公开(公告)号：US20060148154A1

公开(公告)日：2006-07-06

申请号：US11281599

申请日：2005-11-18

申请人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

发明人： Dong-Suk Shin ,  Ueno Tetsuji ,  Seung-Hwan Lee ,  Ho Lee ,  Hwa-Sung Rhee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

摘要翻译： 公开了用于制造用于制造半导体器件，特别是CMOS器件的半导体衬底的工艺和技术，其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据，NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能，并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

公开(公告)号：US07582535B2

公开(公告)日：2009-09-01

申请号：US11158978

申请日：2005-06-22

申请人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

发明人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.

摘要翻译： 提供制造具有完全硅化金属栅电极的MOS晶体管的方法。 该方法包括在半导体衬底的预定区域中形成隔离层以限定有源区。 形成了跨越有源区域的绝缘栅极图案。 在栅极图案的侧壁上形成间隔物。 施加选择性外延生长工艺以在栅极图案上形成半导体层，并且在栅极图案的两侧形成半导体层。 在这种情况下，在栅极图案上形成多晶半导体层，同时在栅极图案的两侧的有源区同时形成单晶半导体层。 选择性地蚀刻半导体层以形成栅极减小图案和升高的源极和漏极区域。 可以使用多晶半导体层和单晶半导体层之间的蚀刻选择性来获得栅极减小图案和升高的源极和漏极区域的各种期望厚度。 将硅化处理应用于形成栅极减少图案的半导体衬底，以同时形成完全硅化的金属栅电极和升高的源极和漏极硅化物层。

公开(公告)号：US20060038243A1

公开(公告)日：2006-02-23

申请号：US11071018

申请日：2005-03-03

申请人： Tetsuji Ueno ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

发明人： Tetsuji Ueno ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66621 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/045 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659

摘要： A transistor of the present invention includes a semiconductor substrate that has a first surface of the {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a side face of the {111} crystal plane connecting the first surface to the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the side face. Impurity regions are formed adjacent to both sides of the gate structure. The impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

摘要翻译： 本发明的晶体管包括半导体衬底，其具有{100}晶面的第一表面，{100}晶面的第二表面的高度低于第一表面的高度，并且 {111}晶面将第一表面连接到第二表面。 栅极结构形成在第一表面上。 在第二表面和侧面上形成外延层。 杂质区域形成在栅极结构的两侧附近。 杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

公开(公告)号：US07714394B2

公开(公告)日：2010-05-11

申请号：US11285978

申请日：2005-11-23

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L23/58

CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

公开(公告)号：US07361563B2

公开(公告)日：2008-04-22

申请号：US11299447

申请日：2005-12-09

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/205 ,  H01L29/80 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

公开(公告)号：US20050279997A1

公开(公告)日：2005-12-22

申请号：US11154236

申请日：2005-06-16

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L21/28044 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/66772

摘要： In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

摘要翻译： 在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中，单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶 半导体图案，分别使用主半导体源气体和主蚀刻气体。 使用选择性蚀刻气体去除非单晶外延半导体层。 主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。 选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

公开(公告)号：US07601983B2

公开(公告)日：2009-10-13

申请号：US11207703

申请日：2005-08-19

申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/66636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

摘要翻译： 晶体管包括具有{100}晶面的第一表面，{100}晶面的第二表面的半导体衬底的高度低于第一表面的第一表面，以及{111}晶体的第三表面 将第一表面连接到第二表面的平面。 在第二表面下形成第一重掺杂杂质区。 栅极结构形成在第一表面上。 在第二表面和第三表面上形成外延层。 在栅极结构的两侧形成第二重掺杂杂质区。 第二重掺杂杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。