公开(公告)号：US20140252557A1

公开(公告)日：2014-09-11

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/308 ,  H01L29/06

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20140231907A1

公开(公告)日：2014-08-21

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

公开(公告)号：US20140191332A1

公开(公告)日：2014-07-10

申请号：US14208423

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Stephan Kronholz ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/10 ,  H01L27/108

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L27/108 ,  H01L27/10894 ,  H01L29/1033

Abstract: Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.

Abstract translation: 本文公开了一种器件，其包括形成在半导体衬底的第一有源区中和上方的第一PFET晶体管，形成在半导体衬底的第二有源区中和之上的第二PFET晶体管，其中， 第一和第二沟道半导体材料或第一和第二沟道半导体材料中的锗浓度不同。

公开(公告)号：US20140167119A1

公开(公告)日：2014-06-19

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L29/78 ,  H01L21/314

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US08722481B2

公开(公告)日：2014-05-13

申请号：US13909221

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L22/10 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7848 ,  Y02P80/30

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract translation: 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。