公开(公告)号：US09006835B2

公开(公告)日：2015-04-14

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US08969916B2

公开(公告)日：2015-03-03

申请号：US14447830

申请日：2014-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC: H01L27/092 ,  H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

Abstract translation: 半导体器件包括晶体管的栅极电极结构，栅极电极结构位于半导体区域之上并具有包括高k介电材料的栅极绝缘层，位于栅极绝缘层上方的含金属盖材料， 以及位于含金属盖材料上方的栅电极材料。 栅电极结构的底部具有第一长度，并且栅电极结构的上部具有与第一长度不同的第二长度，其中第一长度为约50nm或更小。 应变诱导半导体合金嵌入在与栅电极结构的底部相邻的半导体区域中，并且漏极和源极区域至少部分地位于应变诱导半导体合金中。

公开(公告)号：US20160071978A1

公开(公告)日：2016-03-10

申请号：US14944833

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Abstract translation: 半导体器件包括位于晶体管的有源区域中的漏极和源极区域以及横向设置在漏极和源极区域之间的沟道区域，该沟道区域包括位于半导体基底材料上的半导体基底材料和阈值电压调节半导体材料。 门极电极结构位于阈值电压调节用半导体材料上，并且包含位于第一半导体材料上方的第一半导体材料和第二半导体材料的应变诱发半导体合金嵌入有源区的半导体基底材料中。 第三半导体材料的结晶缓冲层包围嵌入式应变诱导半导体合金，其中结晶缓冲层的上部横向限制包括阈值电压调节半导体材料的侧壁的沟道区，并且位于第二半导体材料 和阈值电压调节半导体材料。

公开(公告)号：US09029919B2

公开(公告)日：2015-05-12

申请号：US13757205

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Joachim Patzer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

Abstract translation: 这里公开了在晶体管的源极/漏极区之上形成硅/锗保护层的各种方法。 本文公开的一种方法包括在靠近栅极结构的衬底中形成多个凹槽，在凹槽中形成半导体材料，在半导体材料上形成至少一层硅，并在层上形成由硅锗组成的覆盖层 的硅。 本文公开的一种装置包括位于衬底上方的栅极结构，在栅极结构附近形成在衬底中的多个凹槽，至少部分地位于凹部中的至少一层半导体材料，位于至少至少 一层半导体材料，以及由位于硅层上的硅/锗组成的覆盖层。

公开(公告)号：US20140131805A1

公开(公告)日：2014-05-15

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US20130221540A1

公开(公告)日：2013-08-29

申请号：US13858198

申请日：2013-04-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/8221 ,  H01L23/53276 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/80001

Abstract: In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

Abstract translation: 在堆叠式芯片配置中，基于功能分子建立“芯片间”连接，从而在不同半导体芯片之间提供快速且空间有效的通信。

公开(公告)号：US09263582B2

公开(公告)日：2016-02-16

申请号：US14502428

申请日：2014-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Maciej Wiatr

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L27/20 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/20 ,  H01L29/7843

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract translation: 可以基于压电材料提供有效的应变诱导机构，从而通过应用单个概念可以提高不同晶体管类型的性能。 例如，压电材料可以设置在不同晶体管类型的有源区的下方，并且可以适当地连接到电压源，以便获得期望的类型的应变。

公开(公告)号：US20150054083A1

公开(公告)日：2015-02-26

申请号：US14502428

申请日：2014-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/7849 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/20 ,  H01L29/7843

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract translation: 可以基于压电材料提供有效的应变诱导机构，从而通过应用单个概念可以提高不同晶体管类型的性能。 例如，压电材料可以设置在不同晶体管类型的有源区的下方，并且可以适当地连接到电压源，以便获得期望的类型的应变。

公开(公告)号：US20140339604A1

公开(公告)日：2014-11-20

申请号：US14447830

申请日：2014-07-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

Abstract translation: 半导体器件包括晶体管的栅极电极结构，栅极电极结构位于半导体区域之上并具有包括高k介电材料的栅极绝缘层，位于栅极绝缘层上方的含金属盖材料， 以及位于含金属盖材料上方的栅电极材料。 栅电极结构的底部具有第一长度，并且栅电极结构的上部具有与第一长度不同的第二长度，其中第一长度为约50nm或更小。 应变诱导半导体合金嵌入在与栅电极结构的底部相邻的半导体区域中，并且漏极和源极区域至少部分地位于应变诱导半导体合金中。

公开(公告)号：US08847404B2

公开(公告)日：2014-09-30

申请号：US13858198

申请日：2013-04-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/8221 ,  H01L23/53276 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/80001

Abstract: In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

Abstract translation: 在堆叠式芯片配置中，基于功能分子建立“芯片间”连接，从而在不同半导体芯片之间提供快速且空间有效的通信。