公开(公告)号：US06989715B2

公开(公告)日：2006-01-24

申请号：US11057968

申请日：2005-02-15

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03F3/45

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract translation: 本发明的方面提供了快速的一级零电流状态异或门。 本发明的实施例提供了第一对差分配置的晶体管和耦合到第一对差分配置的晶体管的电平转换电阻器。 一级零电流状态XOR门还可以包括第二对差分配置的晶体管。 XOR门的核可以耦合到第一对和第二对差分配置的晶体管的输出。

公开(公告)号：US06943587B2

公开(公告)日：2005-09-13

申请号：US10448640

申请日：2003-05-30

Applicant: Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

Inventor： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC: H03K19/0185 ,  H04L7/00 ,  H03K19/0175

CPC classification number: H03K19/018585 ,  H04L7/0008

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract translation: 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US06930512B2

公开(公告)日：2005-08-16

申请号：US10456804

申请日：2003-06-06

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

公开(公告)号：US20050162208A1

公开(公告)日：2005-07-28

申请号：US11084369

申请日：2005-03-18

Applicant: Bo Zhang ,  Guangming Yin

Inventor： Bo Zhang ,  Guangming Yin

IPC: H03H11/12 ,  H03H11/26

CPC classification number: H03H11/265 ,  H03H11/126

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract translation: 延迟电路产生延迟信号。 延迟电路包括具有耦合到周期性输入信号的输入端的延迟锁定环，延迟锁定产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和与来自延迟锁存器的控制信号耦合的延迟控制端子，用于控制接收到的延迟的周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。

公开(公告)号：US06897697B2

公开(公告)日：2005-05-24

申请号：US10229257

申请日：2002-08-26

Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

IPC: H03K3/356 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/094 ,  H03K19/21

CPC classification number: H03K3/3562 ,  H03K3/356043 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

公开(公告)号：US06870415B2

公开(公告)日：2005-03-22

申请号：US10243086

申请日：2002-09-12

Applicant: Bo Zhang ,  Guangming Yin

Inventor： Bo Zhang ,  Guangming Yin

IPC: H03H11/12 ,  H03H11/26

CPC classification number: H03H11/265 ,  H03H11/126

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked loop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked loop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract translation: 延迟电路产生延迟信号。 延迟电路包括延迟锁定环路，其具有耦合到周期性输入信号的输入端子，延迟锁定环路产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和耦合到来自延迟锁定环路的控制信号的延迟控制端子，用于控制接收到的延迟周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。