公开(公告)号：US20190068316A1

公开(公告)日：2019-02-28

申请号：US16163169

申请日：2018-10-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huazi Zhang ,  Jiajie Tong ,  Rong Li ,  Jun Wang ,  Wen Tong ,  Yiqun Ge ,  Xiaocheng Liu ,  Gongzheng Zhang ,  Jian Wang ,  Nan Cheng ,  Qifan Zhang

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/00 ,  H03M13/13

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

公开(公告)号：US10042641B2

公开(公告)日：2018-08-07

申请号：US14480573

申请日：2014-09-08

Applicant: Huawei Technologies Co. Ltd

Inventor： Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Tao Huang ,  Wen Tong

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

公开(公告)号：US20180076929A1

公开(公告)日：2018-03-15

申请号：US15699976

申请日：2017-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huazi Zhang ,  Jiajie Tong ,  Rong Li ,  Jun Wang ,  Wen Tong ,  Yiqun Ge ,  Xiaocheng Liu ,  Gongzheng Zhang ,  Jian Wang ,  Nan Cheng ,  Qifan Zhang

IPC: H04L1/00 ,  H03M13/00

CPC classification number: H04L1/0009 ,  H03M13/11 ,  H03M13/13 ,  H03M13/611 ,  H03M13/616 ,  H03M13/6362 ,  H04L1/0041 ,  H04L1/0043 ,  H04L1/0061 ,  H04L1/0063 ,  H04L1/0065

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.

公开(公告)号：US09846581B2

公开(公告)日：2017-12-19

申请号：US14480556

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Huang ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Wen Tong

IPC: G06F9/38 ,  G06F15/80 ,  G06F15/82 ,  G06F9/30 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

公开(公告)号：US09720880B2

公开(公告)日：2017-08-01

申请号：US14480562

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F15/82 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/825 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

公开(公告)号：US09535698B2

公开(公告)日：2017-01-03

申请号：US14480522

申请日：2014-09-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: G06F9/30 ,  G06F15/76 ,  G06F9/38 ,  G06F1/08 ,  G06F1/10 ,  G06F9/50

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

公开(公告)号：US20240388383A1

公开(公告)日：2024-11-21

申请号：US18785872

申请日：2024-07-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hao Tang ,  Liqing Zhang ,  Jianglei Ma ,  Yiqun Ge ,  Peiying Zhu ,  Wen Tong

IPC: H04L1/1812 ,  H04L1/1829

Abstract: Current online training procedures for artificial intelligence/machine learning (AI/ML) models for wireless communication generally suffer from high communication overhead and/or significant delays in training, particularly when training data is exchanged over an unreliable/hostile communication channel. An example method includes communicating, in accordance with a first communication mode, data or control information with a second device in the wireless communication network. The first communication mode is one of a plurality of communication modes comprising at least the first communication mode and a second communication mode, the second communication mode differing from the first communication mode in terms of at least one of a quantization level used to quantize values of variables in the data or control information, or a Hybrid Automatic Repeat reQuest (HARQ) feedback and retransmission mode for selective retransmission of one or more portions of the data or control information.

公开(公告)号：US11343014B2

公开(公告)日：2022-05-24

申请号：US16824658

申请日：2020-03-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jian Wang ,  Huangping Jin ,  Shengchen Dai ,  Rong Li ,  Yinggang Du ,  Jun Wang ,  Yiqun Ge

IPC: H04L12/28 ,  H04L1/00 ,  H04B7/06 ,  H04J1/16

Abstract: The application provides method for communicating channel state information (CSI) in a communication network. The method is as follows: An apparatus determines whether a length of CSI is less than a preset length; and adds a padding bit to the CSI when determining that the length of the CSI is less than the preset length, where a length of CSI obtained by adding the padding bit is consistent with the predetermined length. The CSI obtained by adding the padding bit is communicated in the communication network.

公开(公告)号：US20210328600A1

公开(公告)日：2021-10-21

申请号：US17363091

申请日：2021-06-30

Applicant: Huawei Technologies Co., Ltd. ,  The Royal Institution for the Advancement of Learning/McGill University

Inventor： Warren Jeffrey Gross ,  Adam Christian Cavatassi ,  Thibaud Tonnellier ,  Yiqun Ge

IPC: H03M13/13 ,  H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs). For the most part, the provided embodiments can be implemented with nearly all available current encoding/decoding polar code techniques

公开(公告)号：US11057053B2

公开(公告)日：2021-07-06

申请号：US16569813

申请日：2019-09-13

Applicant: Huawei Technologies Co., Ltd. ,  THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY

Inventor： Warren Jeffrey Gross ,  Adam Christian Cavatassi ,  Thibaud Tonnellier ,  Yiqun Ge

IPC: H03M13/13 ,  H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs). For the most part, the provided embodiments can be implemented with nearly all available current encoding/decoding polar code techniques.