公开(公告)号：US08492206B2

公开(公告)日：2013-07-23

申请号：US13375692

申请日：2011-08-29

申请人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L21/335 ,  H01L21/70

CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

摘要翻译： 公开了一种半导体器件结构及其制造方法。 在一个实施例中，所述方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US20130093041A1

公开(公告)日：2013-04-18

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US20130049125A1

公开(公告)日：2013-02-28

申请号：US13375692

申请日：2011-08-29

申请人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

发明人： Huicai Zhong ,  Jun Luo ,  Qingqing Liang ,  Huilong Zhu

IPC分类号： H01L27/088 ,  H01L21/283

CPC分类号： H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1211

摘要： A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

摘要翻译： 公开了一种半导体器件结构及其制造方法。 在一个实施例中，该方法包括：在半导体衬底上沿第一方向形成翅片; 在半导体衬底上与第一方向交叉的第二方向上形成栅极线，栅极线经由栅极电介质层与鳍状物相交; 形成围绕所述栅极线的介电隔离层; 形成围绕所述电介质间隔物的导电间隔物; 以及在预定区域执行器件间电隔离，其中栅极线的隔离部分形成各个单元器件的栅电极，并且导电间隔物的隔离部分形成各个单元器件的接触。

公开(公告)号：US20130049092A1

公开(公告)日：2013-02-28

申请号：US13501518

申请日：2011-11-18

申请人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Miao Xu ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L29/786 ,  H01L29/78

CPC分类号： H01L29/78654 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.

摘要翻译： 本申请公开了一种包括超薄半导体层中的源极区域和漏极区域的半导体器件; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和所述沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极 由低Vt材料制成。 根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。 半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

公开(公告)号：US20130020578A1

公开(公告)日：2013-01-24

申请号：US13521998

申请日：2011-11-30

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：布置在绝缘层上的有源鳍片区域; 设置在有源鳍片区域顶部的阈值电压调整层，该阈值电压调整层用于调整半导体器件的阈值电压; 栅极堆叠，其布置在阈值电压调节层上，在有源鳍片区域的侧壁和绝缘层上，并且包括形成在栅极电介质上的栅极电介质和栅电极; 以及分别形成在栅极堆叠两侧的有源鳍片区域中的源极区域和漏极区域。 根据本发明的半导体器件包括可调节半导体器件的阈值电压的阈值电压调节层。 这提供了能够调整包括有源鳍片区域的半导体器件的阈值电压的简单且方便的方式。

公开(公告)号：US20120319185A1

公开(公告)日：2012-12-20

申请号：US13063653

申请日：2010-06-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced.

摘要翻译： 本发明提供了一种NAND门结构，包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在所述基板中的源极/漏极区域; 形成在栅极绝缘体层上的中间栅极，在中间栅极的每一侧上的第一栅极和第二栅极，第一栅极和中间栅极之间以及第二栅极和中间栅极之间的第一侧壁间隔物，以及第二侧壁间隔物 在第一栅极和第二栅极之外，其中，第一接触孔区域设置在中间栅极上，第二接触孔区域分别设置在第一栅极和第二栅极上，第一接触孔区域和第二接触孔 地区交错排列。 本发明提出了一种新的NAND结构及其制造方法。 利用NAND结构，芯片面积的30-50％可以有效降低。

公开(公告)号：US20120286337A1

公开(公告)日：2012-11-15

申请号：US13377141

申请日：2011-08-10

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/1211 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66545

摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.

摘要翻译： 本发明的实施例公开了一种制造Fin场效应晶体管的方法。 当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层， 然后，通过间隔物在伪栅极的两侧形成自对准和升高的源/漏区，其中栅极和源极/漏极区的上表面在同一平面内。 栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

公开(公告)号：US20120043624A1

公开(公告)日：2012-02-23

申请号：US13132535

申请日：2011-01-27

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/78654 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

摘要翻译： 公开了一种超薄体晶体管和制造超薄体晶体管的方法。 超薄体晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及半导体衬底中的栅极结构的任一侧上的源极区和漏极区; 其中栅极结构包括栅极电介质层，嵌入栅极电介质层中的栅极和栅极两侧的间隔物; 所述超薄体晶体管还包括：主体区域和位于所述栅极结构之下且位于阱区域中的掩埋绝缘区域; 主体区域和埋入绝缘区域的两端分别与源极区域和漏极区域连接; 并且身体区域通过身体区域下的埋入绝缘区域与阱区域中的其它区域隔离。 超薄体晶体管具有较薄的体区，从而降低了短沟道效应。 在与替换栅极工艺一起制造超薄体晶体管的方法中，掩埋绝缘区域的形成与栅极自对准，这降低了间隔物下的寄生电阻。

公开(公告)号：US20090073758A1

公开(公告)日：2009-03-19

申请号：US11857757

申请日：2007-09-19

申请人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

发明人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： G11C11/34 ,  H01L21/00

CPC分类号： G11C11/412

摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.

摘要翻译： 本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。 更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。 第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。 第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。 第二通栅晶体管包括第二源区和第二漏区。 此外，第一源区和/或第二源区包括氙植入物。 第一漏区和第二漏区各自缺少氙植入物。

公开(公告)号：US07485521B2

公开(公告)日：2009-02-03

申请号：US11160676

申请日：2005-07-05

申请人： Huilong Zhu ,  Brian L. Tessier ,  Huicai Zhong

发明人： Huilong Zhu ,  Brian L. Tessier ,  Huicai Zhong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7843 ,  Y10S438/938

摘要： Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.

摘要翻译： 公开了用于形成用于增强NFET和PFET的性能的自对准双应力层的方法。 在一个实施例中，牺牲层用于去除先前沉积的应力层。 调整用于图案化牺牲层的掩模位置，使得使用牺牲层去除后者沉积的应力层以对准的形式离开双应力层。 这种方法导致双重应力层不重叠或不重叠，从而避免了由这些问题产生的处理问题。 还公开了包括对准的双重应力层的半导体器件。