公开(公告)号：US07771764B2

公开(公告)日：2010-08-10

申请号：US10543891

申请日：2004-01-30

申请人： Takeshi Honda ,  Takeshi Imazawa ,  Takamune Tanaka ,  Takao Tomita ,  Yasushi Kubota ,  Naoki Orii ,  Tadashi Nakatsubo

发明人： Takeshi Honda ,  Takeshi Imazawa ,  Takamune Tanaka ,  Takao Tomita ,  Yasushi Kubota ,  Naoki Orii ,  Tadashi Nakatsubo

IPC分类号： A23F5/00

CPC分类号： A23F5/48 ,  A23F3/16 ,  A23F3/18 ,  A23F5/24 ,  A23F5/265 ,  A23L2/02 ,  A23L2/04 ,  A23L27/11

摘要： A method for producing an extract and/or a squeezed liquid, which includes: feeding a food to be extracted and/or squeezed into a crushing apparatus; adding a solvent into the crushing apparatus immediately after and/or while milling the food; extracting and/or squeezing a useful food component of the food into the solvent; and carrying out liquid-solid separation by removing the resulting extracted residue and/or squeezed residue with a continuous solid-liquid separation apparatus.

摘要翻译： 一种提取物和/或挤压液体的制造方法，其特征在于，包括：将要提取和/或挤压的食品送入破碎装置; 在粉碎食物之后和/或同时在粉碎设备中加入溶剂; 将食物的有用食物成分提取和/或挤压到溶剂中; 并通过用连续的固液分离装置除去所得的萃取残渣和/或挤压的残留物进行液固分离。

公开(公告)号：US07714827B2

公开(公告)日：2010-05-11

申请号：US10717235

申请日：2003-11-18

申请人： Yasushi Kubota ,  Seiji Murakami

发明人： Yasushi Kubota ,  Seiji Murakami

IPC分类号： G09G3/36

CPC分类号： G09G3/3266 ,  G09G3/20 ,  G09G3/3208 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/08

摘要： An integrated circuit is provided for scan driving that can significantly reduce the chip size. In first region AODD, odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175, driver circuits DR1, DR3, . . . DR173, DR175, and flip-flops SREG1, SREG3, . . . SREG173, SREG175 in an order corresponding to the order of the odd-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction). In second region AEVEN, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176, driver circuits DR2, DR4, . . . DR174, DR176, and flip-flops SREG2, SREG4, . . . SREG174, SREG176 in an order corresponding to the order of the even-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction).

摘要翻译： 提供了可以显着降低芯片尺寸的扫描驱动的集成电路。 在第一区域AODD中，奇数编号的输出焊盘OUT1，OUT3，...。 。 。 OUT173，OUT175，驱动电路DR1，DR3，。 。 。 DR173，DR175和触发器SREG1，SREG3，。 。 。 SREG173，SREG175以与奇数扫描线的顺序对应的顺序分别排列成X方向的列，并且同时，输出焊盘OUTi，驱动电路DRi和触发器SREGi对应于 扫描线在Y方向（芯片宽度方向）排列成同一行。 在第二区域AEVEN中，偶数输出焊盘OUT2，OUT4。 。 。 OUT174，OUT176，驱动电路DR2，DR4，。 。 。 DR174，DR176和触发器SREG2，SREG4， 。 。 SREG174，SREG176以与偶数扫描线的顺序相对应的顺序分别排列成X方向的列，并且同时，输出焊盘OUTi，驱动电路DRi和触发器SREGi对应于 扫描线在Y方向（芯片宽度方向）排列成同一行。

公开(公告)号：US07713563B2

公开(公告)日：2010-05-11

申请号：US10538298

申请日：2003-12-10

申请人： Yasushi Kubota ,  Yukinari Takeuchi ,  Satoshi Hayashi ,  Naoki Orii ,  Tadashi Nakatsubo

发明人： Yasushi Kubota ,  Yukinari Takeuchi ,  Satoshi Hayashi ,  Naoki Orii ,  Tadashi Nakatsubo

IPC分类号： A23C9/00

CPC分类号： A23C9/1524 ,  A23C3/03 ,  A23C17/00 ,  A23C2240/20

摘要： A process for preparing butter milk and/or butter serum, which comprises decreasing the dissolved oxygen concentration of at least one selected from the group consisting of milk, a milk product, butter milk and butter serum, followed by heating, and optionally fractionizing the heated product.

摘要翻译： 一种制备奶油和/或黄油血清的方法，其包括降低选自牛奶，奶制品，奶油和黄油血清中的至少一种的溶解氧浓度，然后加热，并且任选地将加热的 产品。

公开(公告)号：US20090238926A1

公开(公告)日：2009-09-24

申请号：US12094432

申请日：2006-11-20

申请人： Tomokazu Hara ,  Tomoyasu Taguchi ,  Yasushi Kubota

发明人： Tomokazu Hara ,  Tomoyasu Taguchi ,  Yasushi Kubota

IPC分类号： A23C3/00 ,  B65D85/72 ,  A23C7/04

CPC分类号： B65D81/30 ,  A23C3/005 ,  A23G9/00 ,  B65D65/20 ,  B65D85/80

摘要： An object of the present invention is to provide a milk-type food and drink including cow's milk packed in a transparent container such as a PET bottle, which does not generate off-flavor due to photoinduction even when the milk-type food and drink is a store-displaying commercial product which is apt to come under the influence of sunlight and fluorescent light. The invention relates to a milk-type food and drink packed in a transparent container which substantially shields light in the wavelength region of 550 to 720 nm, and a process for producing a milk-type food and drink, which comprises packing a milk-type food and drink in a transparent container which substantially shields light in the wavelength region of 550 to 720 nm.

摘要翻译： 本发明的目的是提供一种包含牛奶的奶类食品和饮料，其包装在诸如PET瓶的透明容器中，即使当乳型食品和饮料是 一种容易受到阳光和荧光灯影响的商店展示商品。 本发明涉及一种包装在透明容器中的乳状食品和饮料，其基本上屏蔽了550-720nm的波长范围的光，以及一种生产牛奶型食品和饮料的方法，包括将牛奶型 在透明容器中食物和饮料，其基本上屏蔽在550至720nm的波长区域中的光。

公开(公告)号：US07460099B2

公开(公告)日：2008-12-02

申请号：US10949990

申请日：2004-09-23

申请人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

发明人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/021 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

公开(公告)号：US20080150924A1

公开(公告)日：2008-06-26

申请号：US12071529

申请日：2008-02-21

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G06F3/038 ,  H03K19/0175

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

公开(公告)号：US07365727B2

公开(公告)日：2008-04-29

申请号：US10788161

申请日：2004-02-25

申请人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Masakazu Satoh ,  Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0283 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/28

摘要： A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease. Consequently, there can be provided a shift register that is capable of shifting in two directions, that can normally operate even with an input signal having a small amplitude, and that therefore consumes less electric power.

摘要翻译： 移位寄存器具有移位寄存器部分，该移位寄存器部分由与时钟信号同步操作的多级触发器组成;以及电平移位器，用于升压低于驱动电压的启动信号，并将其施加到两端 的移位寄存器，并且移位寄存器能够根据切换信号切换移位方向。 上述电平移位器是电流驱动型电平移位器，即使在晶体管特性较差的情况下或者在快速操作的情况下也能够工作，并且即使利用具有小振幅的启动信号也能进行电平移位。 此外，上述电平移位器分别设置在移位寄存器部分的两端，并且其中一个电平移位器根据切换信号停止工作，从而消耗的功率应该减小。 因此，可以提供能够在两个方向上移位的移位寄存器，即使在具有小幅度的输入信号的情况下也能正常地进行操作，因此消耗较少的电力。

公开(公告)号：US07358950B2

公开(公告)日：2008-04-15

申请号：US10145905

申请日：2002-05-16

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

公开(公告)号：US07193604B2

公开(公告)日：2007-03-20

申请号：US11060963

申请日：2005-02-18

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

公开(公告)号：US20060057271A1

公开(公告)日：2006-03-16

申请号：US10538298

申请日：2003-12-10

申请人： Yasushi Kubota ,  Yukinari Takeuchi ,  Satoshi Hayashi ,  Naoki Orii ,  Tadashi Nakatsubo

发明人： Yasushi Kubota ,  Yukinari Takeuchi ,  Satoshi Hayashi ,  Naoki Orii ,  Tadashi Nakatsubo

IPC分类号： A23C21/00

CPC分类号： A23C9/1524 ,  A23C3/03 ,  A23C17/00 ,  A23C2240/20

摘要： A process for preparing butter milk and/or butter serum, which comprises decreasing the dissolved oxygen concentration of at least one selected from the group consisting of milk, a milk product, butter milk and butter serum, followed by heating, and optionally fractionizing the heated product.

摘要翻译： 一种制备奶油和/或黄油血清的方法，其包括降低选自牛奶，奶制品，奶油和黄油血清中的至少一种的溶解氧浓度，然后加热，并且任选地将加热的 产品。