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    Fast voltage regulators for charge pumps
    52.
    发明授权
    Fast voltage regulators for charge pumps 有权
    快速电压调节器

    公开(公告)号：US07868604B2

    公开(公告)日：2011-01-11

    申请号：US11941964

    申请日：2007-11-18

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    IPC分类号： H02M3/18

    CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

    摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

    摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

    ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS
    54.
    发明申请
    ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS 有权
    非易失性记忆细胞的阵列和位点

    公开(公告)号：US20100188900A1

    公开(公告)日：2010-07-29

    申请号：US12362106

    申请日：2009-01-29

    申请人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

    发明人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C16/0408

    摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.

    摘要翻译： 一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子 在一定操作期间提供，并且在所有操作中提供低电压的第三端子。 同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。 阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。 第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。 第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。 第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。 与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。 低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

    Fast voltage regulators for charge pumps
    55.
    发明授权
    Fast voltage regulators for charge pumps 有权
    快速电压调节器

    公开(公告)号：US07728563B2

    公开(公告)日：2010-06-01

    申请号：US12340571

    申请日：2008-12-19

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung O. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    IPC分类号： G05F1/613

    CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

    摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

    摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

    Sub volt flash memory system
    57.
    发明授权
    Sub volt flash memory system 有权
    亚伏闪存系统

    公开(公告)号：US08300494B2

    公开(公告)日：2012-10-30

    申请号：US12980209

    申请日：2010-12-28

    申请人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

    发明人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

    IPC分类号： G11C8/00

    CPC分类号： G11C16/28 ,  G11C16/08 ,  G11C16/30

    摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

    摘要翻译： 各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。 可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。 体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。 各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。 电路可以包括在存储器系统中。

    Sub volt flash memory system
    58.
    发明授权
    Sub volt flash memory system 有权
    亚伏闪存系统

    公开(公告)号：US07990773B2

    公开(公告)日：2011-08-02

    申请号：US12623306

    申请日：2009-11-20

    申请人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

    发明人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/28 ,  G11C16/08 ,  G11C16/30

    摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

    摘要翻译： 各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。 可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。 体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。 各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。 电路可以包括在存储器系统中。

    Array and pitch of non-volatile memory cells
    59.
    发明授权
    Array and pitch of non-volatile memory cells 有权
    非易失性存储单元的阵列和间距

    公开(公告)号：US07839682B2

    公开(公告)日：2010-11-23

    申请号：US12362106

    申请日：2009-01-29

    申请人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

    发明人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

    IPC分类号： G11C16/00

    CPC分类号： G11C16/10 ,  G11C16/0408

    摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.

    摘要翻译： 一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子 在一定操作期间提供，并且在所有操作中提供低电压的第三端子。 同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。 阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。 第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。 第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。 第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。 与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。 低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

    Fast Start Charge Pump for Voltage Regulators
    60.
    发明申请
    Fast Start Charge Pump for Voltage Regulators 有权
    用于稳压器的快速启动电荷泵

    公开(公告)号：US20100188138A1

    公开(公告)日：2010-07-29

    申请号：US12726249

    申请日：2010-03-17

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu AAron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu AAron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    IPC分类号： G05F1/10

    CPC分类号： H02M3/07 ,  H02M1/36 ,  H02M1/44

    摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

    摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。