公开(公告)号：US08669145B2

公开(公告)日：2014-03-11

申请号：US10710272

申请日：2004-06-30

申请人： Bruce B. Doris ,  Diane C. Boyd ,  Huilong Zhu

发明人： Bruce B. Doris ,  Diane C. Boyd ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/7842

摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.

摘要翻译： 形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

公开(公告)号：US08013392B2

公开(公告)日：2011-09-06

申请号：US11863757

申请日：2007-09-28

申请人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

IPC分类号： H01L27/01

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

摘要翻译： 在衬底上形成的半导体结构和形成半导体的工艺。 半导体包括具有场效应晶体管（FETS）的第一部分和场效应晶体管的第二部分的多个场效应晶体管。 第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。 第二应力层具有第二厚度，并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。

公开(公告)号：US07723791B2

公开(公告)日：2010-05-25

申请号：US12192573

申请日：2008-08-15

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen ,  Patricia M. Mooney ,  Stephen W. Bedell

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen ,  Patricia M. Mooney ,  Stephen W. Bedell

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

摘要翻译： 本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。 广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

公开(公告)号：US07713806B2

公开(公告)日：2010-05-11

申请号：US12352504

申请日：2009-01-12

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

公开(公告)号：US20080142852A1

公开(公告)日：2008-06-19

申请号：US12032913

申请日：2008-02-18

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L27/092

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。

公开(公告)号：US07224033B2

公开(公告)日：2007-05-29

申请号：US10906335

申请日：2005-02-15

申请人： Huilong Zhu ,  Bruce B. Doris

发明人： Huilong Zhu ,  Bruce B. Doris

IPC分类号： H01L29/76 ,  H01L23/62 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7842 ,  H01L29/7854 ,  H01L29/78645 ,  H01L2924/0002 ,  H01L2924/00

摘要： A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

摘要翻译： FINFET栅极的一部分由应力材料代替，以对FINFET的沟道施加应力，以增强电子和空穴的迁移率并提高性能。 FINFET具有SiGe / Si堆叠栅极，并且在硅化之前，选择性地蚀刻栅极的SiGe部分以形成栅极间隙，使得栅极足够薄以完全硅化。 在硅化之后，栅间隙填充有应力氮化物膜，以在沟道中产生应力并增强FINFET的性能。

公开(公告)号：US07173312B2

公开(公告)日：2007-02-06

申请号：US10905101

申请日：2004-12-15

申请人： Cyril Cabral, Jr. ,  Bruce B. Doris ,  Thomas S. Kanarsky ,  Xiao H. Liu ,  Huilong Zhu

发明人： Cyril Cabral, Jr. ,  Bruce B. Doris ,  Thomas S. Kanarsky ,  Xiao H. Liu ,  Huilong Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

公开(公告)号：US07015082B2

公开(公告)日：2006-03-21

申请号：US10701526

申请日：2003-11-06

申请人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8237 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： A semiconductor device has selectively applied thin tensile films and thin compressive films, as well as thick tensile films and thick compressive films, to enhance electron and hole mobility in CMOS circuits. Fabrication entails steps of applying each film, and selectively removing each applied film from areas that would not experience performance benefit from the applied stressed film.

摘要翻译： 半导体器件已经选择性地施加薄的拉伸膜和薄的压缩膜，以及厚的拉伸膜和厚的压缩膜，以增强CMOS电路中的电子和空穴迁移率。 制造需要施加每个膜的步骤，并且从施加的应力膜不会经历性能的区域中选择性地去除每个施加的膜。

公开(公告)号：US20050189589A1

公开(公告)日：2005-09-01

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20080090366A1

公开(公告)日：2008-04-17

申请号：US11870436

申请日：2007-10-11

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。