公开(公告)号：US20240258382A1

公开(公告)日：2024-08-01

申请号：US18442743

申请日：2024-02-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US11817482B2

公开(公告)日：2023-11-14

申请号：US16997980

申请日：2020-08-20

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Carsten Ahrens ,  Matthias Zigldrum

IPC: H01L29/78 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7786

Abstract: A semiconductor device includes a composite layer having a first and second opposing surfaces. The composite layer includes a mesa and a first insulating layer. The mesa has top and bottom surfaces and side faces. The side faces are embedded in the first insulating layer. The mesa includes a Group III nitride-based multilayer structure providing a Group III nitride based device having first and second electrodes arranged on the mesa top surface. First and second outer contacts are positioned on the second surface of the composite layer. A first conductive via extends through the first insulating layer and is electrically coupled to the first electrode on the mesa top surface and to the first outer contact. A second conductive via extends through the first insulating layer and is electrically coupled to the second electrode on the mesa top surface and to the second outer contact.

公开(公告)号：US20220254913A1

公开(公告)日：2022-08-11

申请号：US17733009

申请日：2022-04-29

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US20210384318A1

公开(公告)日：2021-12-09

申请号：US16894223

申请日：2020-06-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L29/417 ,  H01L21/265 ,  H01L29/205 ,  H01L23/29 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778 ,  H01L21/268

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

公开(公告)号：US20210226039A1

公开(公告)日：2021-07-22

申请号：US17145507

申请日：2021-01-11

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778 ,  H01L21/02 ,  H01L21/78

Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.

公开(公告)号：US20210057528A1

公开(公告)日：2021-02-25

申请号：US16997980

申请日：2020-08-20

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Carsten Ahrens ,  Matthias Zigldrum

IPC: H01L29/20 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes a composite layer having a first and second opposing surfaces. The composite layer includes a mesa and a first insulating layer. The mesa has top and bottom surfaces and side faces. The side faces are embedded in the first insulating layer. The mesa includes a Group III nitride-based multilayer structure providing a Group III nitride based device having first and second electrodes arranged on the mesa top surface. First and second outer contacts are positioned on the second surface of the composite layer. A first conductive via extends through the first insulating layer and is electrically coupled to the first electrode on the mesa top surface and to the first outer contact. A second conductive via extends through the first insulating layer and is electrically coupled to the second electrode on the mesa top surface and to the second outer contact.

公开(公告)号：US20200176594A1

公开(公告)日：2020-06-04

申请号：US16697490

申请日：2019-11-27

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/207 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/205

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US20190363038A1

公开(公告)日：2019-11-28

申请号：US16535237

申请日：2019-08-08

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L29/417 ,  H01L21/288 ,  H01L23/528

Abstract: A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

公开(公告)号：US10242932B2

公开(公告)日：2019-03-26

申请号：US15191989

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines sidewalls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source.

公开(公告)号：US10134603B2

公开(公告)日：2018-11-20

申请号：US15273303

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L21/3105 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/778 ,  H01L29/66

Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarized surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.