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公开(公告)号：US20160119124A1
公开(公告)日：2016-04-28
申请号：US14984601
申请日：2015-12-30
Applicant: Intel Corporation
Inventor： Gueron Shay , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150178083A1
公开(公告)日：2015-06-25
申请号：US14562637
申请日：2014-12-05
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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公开(公告)号：US20150178081A1
公开(公告)日：2015-06-25
申请号：US14562624
申请日：2014-12-05
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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54.发明申请FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) 审中-公开灵活的架构和高级加密标准（AES）公开(公告)号：US20150169474A1
公开(公告)日：2015-06-18
申请号：US14572602
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Abstract translation: 提供了一种用于通用处理器的灵活的指令集。 指令集包括对aes加密或解密执行“一轮”通行的指令，还包括执行密钥生成的指令。 立即可以用于指示128/192/256位键的密钥生成的循环数和密钥大小。 灵活的aes指令集可以充分利用流水线功能，因为它不需要跟踪隐式寄存器。
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公开(公告)号：US20150106594A1
公开(公告)日：2015-04-16
申请号：US14576147
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
CPC classification number: G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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Patent Agency Ranking
公开(公告)号：US20150104010A1
公开(公告)日：2015-04-16
申请号：US14572607
申请日：2014-12-16
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150100797A1
公开(公告)日：2015-04-09
申请号：US14572578
申请日：2014-12-16
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150100796A1
公开(公告)日：2015-04-09
申请号：US14572423
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US11537398B2
公开(公告)日：2022-12-27
申请号：US17341330
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC: G06F9/30 , G06F9/38 , G06F7/06 , G06F12/0875 , G06F9/34
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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公开(公告)号：US11023236B2
公开(公告)日：2021-06-01
申请号：US16458012
申请日：2019-06-29
Applicant: Intel Corporation
Inventor： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC: G06F9/30 , G06F9/38 , G06F7/06 , G06F12/0875 , G06F9/34
Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
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