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公开(公告)号：US08518770B2
公开(公告)日：2013-08-27
申请号：US13628169
申请日：2012-09-27
发明人： Chung-Hsun Lin , Josephine B. Chang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66795 , H01L29/66636 , H01L29/785
摘要： A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h1; reducing the height of the channel structure external to the gate structure so as to have a second height (h2); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.
摘要翻译： 一种制造晶体管的方法，包括在衬底上形成至少一个导电沟道结构，所述沟道具有长度，宽度和第一高度（h1）; 在所述衬底上形成栅极结构，所述栅极结构具有长度，宽度和高度，所述栅极结构垂直于所述沟道结构并且形成在所述沟道结构上，使得所述沟道结构穿过所述栅极结构的宽度 ，其中栅极结构的高度大于h1; 减小栅极结构外部的沟道结构的高度以便具有第二高度（h2）; 以及至少部分地在所述栅极结构外部的所述至少一个沟道结构上沉积硅化物层。
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公开(公告)号：US11133452B2
公开(公告)日：2021-09-28
申请号：US16417711
申请日：2019-05-21
摘要： A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.
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公开(公告)号：US10768155B2
公开(公告)日：2020-09-08
申请号：US16242364
申请日：2019-01-08
IPC分类号： G01N33/00
摘要： The present invention involves a multimodal sensor network for analyte detection. A first mode may involve low-power detection and a second mode may involve determining an analyte concentration and transmitting data associated with the analyte concentration. Specifically, the first mode may include establishing an analyte sensor network in a detection region, detecting an analyte in the detection region, and generating an electrical signal in response to the detecting the analyte. In response to the electrical signal exceeding a first threshold, the analyte detection system may operate in the second mode. The second mode may include requesting data associated with the one or more environmental conditions, determining an analyte concentration based on one or more environmental conditions transmitting data associated with the analyte concentration.
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54.发明授权公开(公告)号：US10680061B2
公开(公告)日：2020-06-09
申请号：US16375218
申请日：2019-04-04
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC分类号： H01L27/12 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/10 , H01L21/84 , H01L29/417 , H01L29/78
摘要： Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
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55.发明申请公开(公告)号：US20200091289A1
公开(公告)日：2020-03-19
申请号：US16690338
申请日：2019-11-21
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/10 , H01L27/12 , H01L29/423 , H01L29/08 , H01L21/84
摘要： Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
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公开(公告)号：US10578571B2
公开(公告)日：2020-03-03
申请号：US16035789
申请日：2018-07-16
发明人： Josephine B. Chang , Hendrik F. Hamann , Siyuan Lu , Xiaoyan Shao
摘要： High-efficiency, ultra-low power gas sensors are provided. In one aspect, a gas detector device is provided which includes: at least one gas sensor having a plurality of fins; a conformal resistive heating element on the fins; a conformal barrier layer on the resistive heating element; and a conformal sensing layer on the barrier layer. A method of forming a gas sensor as well as a method for use thereof in gas detection are also provided.
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57.发明授权公开(公告)号：US10573714B2
公开(公告)日：2020-02-25
申请号：US16100425
申请日：2018-08-10
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC分类号： H01L27/12 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/10 , H01L29/417 , H01L29/78
摘要： Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
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58.发明申请公开(公告)号：US20200028064A1
公开(公告)日：2020-01-23
申请号：US16417711
申请日：2019-05-21
摘要： A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.
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公开(公告)号：US10380494B2
公开(公告)日：2019-08-13
申请号：US15669139
申请日：2017-08-04
IPC分类号： G06N10/00 , G11C11/44 , G11C16/02 , H01L27/18 , H01L39/02 , H01L39/04 , H01L39/22 , H01L39/24 , H03K19/195
摘要： A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.
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公开(公告)号：US20190137468A1
公开(公告)日：2019-05-09
申请号：US16242364
申请日：2019-01-08
IPC分类号： G01N33/00
CPC分类号： G01N33/0075
摘要： The present invention involves a multimodal sensor network for analyte detection. A first mode may involve low-power detection and a second mode may involve determining an analyte concentration and transmitting data associated with the analyte concentration. Specifically, the first mode may include establishing an analyte sensor network in a detection region, detecting an analyte in the detection region, and generating an electrical signal in response to the detecting the analyte. In response to the electrical signal exceeding a first threshold, the analyte detection system may operate in the second mode. The second mode may include requesting data associated with the one or more environmental conditions, determining an analyte concentration based on one or more environmental conditions transmitting data associated with the analyte concentration.
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