公开(公告)号：US10541211B2

公开(公告)日：2020-01-21

申请号：US15486749

申请日：2017-04-13

Applicant: International Business Machines Corporation

Inventor： Tuhin Sinha ,  Krishna R. Tunga

IPC: H01L23/00

Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.

公开(公告)号：US10381276B2

公开(公告)日：2019-08-13

申请号：US14973165

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Sushumna Iruvanti ,  Shidong Li ,  Marek A. Orlowski ,  David L. Questad ,  Tuhin Sinha ,  Krishna R. Tunga ,  Thomas A. Wassick ,  Randall J. Werner ,  Jeffrey A. Zitz

IPC: H01L21/48 ,  G06F17/50 ,  H01L21/66 ,  H01L23/498

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

公开(公告)号：US10276534B2

公开(公告)日：2019-04-30

申请号：US15671955

申请日：2017-08-08

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

公开(公告)号：US20190122574A1

公开(公告)日：2019-04-25

申请号：US15793519

申请日：2017-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mahmoud Amin ,  Zhenxing Bi ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Christopher J. Penny ,  Krishna R. Tunga ,  Loma Vaishnav

IPC: G09B5/02 ,  G09B19/04 ,  G09B19/06 ,  G06F17/28 ,  G10L15/26 ,  G06F17/30

Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning.

公开(公告)号：US10249548B2

公开(公告)日：2019-04-02

申请号：US15813536

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Sushumna Iruvanti ,  Shidong Li ,  Marek A. Orlowski ,  David L. Questad ,  Tuhin Sinha ,  Krishna R. Tunga ,  Thomas A. Wassick ,  Randall J. Werner ,  Jeffrey A. Zitz

IPC: H01L21/00 ,  H01L21/66 ,  G06F17/50 ,  H01L23/498 ,  H01L21/48

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

公开(公告)号：US20180082922A1

公开(公告)日：2018-03-22

申请号：US15791028

申请日：2017-10-23

Applicant: International Business Machines Corporation

Inventor： Kamal K. Sikka ,  Krishna R. Tunga

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/563 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L24/16 ,  H01L2224/16157

Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.

公开(公告)号：US09865557B1

公开(公告)日：2018-01-09

申请号：US15251325

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/17133 ,  H01L2924/3512

Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

公开(公告)号：US20170351783A1

公开(公告)日：2017-12-07

申请号：US15176101

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Vijayeshwar D. Khanna ,  David J. Russell ,  Krishna R. Tunga

IPC: G06F17/50 ,  G06F17/13

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F2217/44 ,  G06F2217/80

Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.