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公开(公告)号：US11251267B2
公开(公告)日：2022-02-15
申请号：US16684022
申请日：2019-11-14
发明人： Zhenxing Bi , Kangguo Cheng , Peng Xu , Zheng Xu
IPC分类号： H01L29/08 , H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/786 , H01L21/8238 , H01L27/092
摘要： A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
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2.发明授权公开(公告)号：US11195754B2
公开(公告)日：2021-12-07
申请号：US16155498
申请日：2018-10-09
发明人： Kangguo Cheng , Zhenxing Bi , Juntao Li , Dexin Kong
IPC分类号： H01L21/768
摘要： A semiconductor structure is provided that includes a gate conductor structure having a middle portion that has a vertical thickness that is greater than a vertical thickness of each end portion, and a self-aligned dielectric gate cap located on the gate conductor structure and having a middle portion that has a vertical thickness that is less than a vertical thickness of each end portion. The aforementioned gate conductor structure, which is taller in the middle and shorter at the edges, has reduced gate resistance, while the aforementioned self-aligned dielectric gate cap, which is taller at the edges and shorter in the middle, increases process margin for contact formation.
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公开(公告)号：US11131919B2
公开(公告)日：2021-09-28
申请号：US16015994
申请日：2018-06-22
发明人： Yongan Xu , Zhenxing Bi , Yann Mignot , Nelson Felix , Ekmini A. De Silva
摘要： A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.
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4.发明申请公开(公告)号：US20210249412A1
公开(公告)日：2021-08-12
申请号：US17242864
申请日：2021-04-28
发明人： Zhenxing Bi , Kangguo Cheng , Juntao Li
IPC分类号： H01L27/092 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/161 , H01L29/49 , H01L21/8238 , H01L29/51 , H01L21/02
摘要： A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.
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公开(公告)号：US10998229B2
公开(公告)日：2021-05-04
申请号：US16173761
申请日：2018-10-29
发明人： Kangguo Cheng , Zhenxing Bi , Juntao Li , Dexin Kong
IPC分类号： H01L29/417 , H01L29/423 , H01L29/66 , H01L21/768 , H01L21/8234 , H01L21/311
摘要： Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.
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公开(公告)号：US20210110727A1
公开(公告)日：2021-04-15
申请号：US17131256
申请日：2020-12-22
发明人： Mahmoud Amin , Zhenxing Bi , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Christopher J. Penny , Krishna R. Tunga , Loma Vaishnav
摘要： A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning. Responsive to the individual being a baby, the voice-to-language processor discretizes baby babbling to consonants, letters, and words.
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公开(公告)号：US10957599B2
公开(公告)日：2021-03-23
申请号：US16182848
申请日：2018-11-07
发明人： Zhenxing Bi , Kangguo Cheng , Junli Wang , Peng Xu
IPC分类号： H01L29/76 , H01L21/8234 , H01L27/088
摘要： Embodiments of the present invention are directed to techniques for integrating an extra gate (EG) vertical field effect transistor (VFET) with a single gate (SG) VFET. In a non-limiting embodiment of the invention, a bottom source or drain (S/D) layer is formed over a substrate. A first semiconductor fin is formed over the bottom S/D layer in a first region of the substrate and a second semiconductor fin is formed over the bottom S/D layer in a second region of the substrate. A block mask is formed over the first semiconductor fin and the second semiconductor fin is recessed. The second semiconductor fin is exposed to an isotropic or anisotropic fin trim.
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公开(公告)号：US20210028175A1
公开(公告)日：2021-01-28
申请号：US17037972
申请日：2020-09-30
发明人： Zhenxing Bi , Zheng Xu , Dexin Kong , Kangguo Cheng
IPC分类号： H01L27/105 , H01L21/8229 , H01L29/06
摘要： A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
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公开(公告)号：US20200273756A1
公开(公告)日：2020-08-27
申请号：US16284261
申请日：2019-02-25
发明人： Kangguo Cheng , Juntao Li , Dexin Kong , Zhenxing Bi
IPC分类号： H01L21/8234 , H01L21/762 , H01L29/66 , H01L27/088
摘要： A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
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公开(公告)号：US10741456B2
公开(公告)日：2020-08-11
申请号：US16156391
申请日：2018-10-10
发明人： Kangguo Cheng , Juntao Li , Zhenxing Bi
摘要： Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.
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