INTEGRATED CIRCUIT IDENTIFICATION AND REVERSE ENGINEERING

    公开(公告)号:US20200082054A1

    公开(公告)日:2020-03-12

    申请号:US16684064

    申请日:2019-11-14

    Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

    METHOD FOR THE CHARACTERIZATION AND MONITORING OF INTEGRATED CIRCUITS

    公开(公告)号:US20190353695A1

    公开(公告)日:2019-11-21

    申请号:US16529398

    申请日:2019-08-01

    Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

    METHOD FOR THE CHARACTERIZATION AND MONITORING OF INTEGRATED CIRCUITS
    56.
    发明申请
    METHOD FOR THE CHARACTERIZATION AND MONITORING OF INTEGRATED CIRCUITS 审中-公开
    集成电路的特征和监测方法

    公开(公告)号:US20170067958A1

    公开(公告)日:2017-03-09

    申请号:US15354095

    申请日:2016-11-17

    Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

    Abstract translation: 一种用于表征集成电路的方法,该集成电路包括使集成电路的电源电压随着集成电路中的每个晶体管的时间而变化,并且在电源电压斜坡期间测量集成电路的电源电流 。 电源电流中测量的峰值是识别每个晶体管处于导通状态的操作状态的电流脉冲。 将电源电流中的峰值与用于具有与集成电路相同功能的参考电路的电源电流的参考峰值进行比较,以确定集成电路的适合度。

    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING
    57.
    发明申请
    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING 有权
    集成时间依赖电介质断开可靠性测试

    公开(公告)号:US20170010322A1

    公开(公告)日:2017-01-12

    申请号:US15258535

    申请日:2016-09-07

    Abstract: Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

    Abstract translation: 用于可靠性测试的系统包括配置成测量被测器件(DUT)上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统,以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置, 在时间上对应于增加的光发射的情况。

    Detection of an aged circuit
    59.
    发明授权

    公开(公告)号:US11879932B2

    公开(公告)日:2024-01-23

    申请号:US16169699

    申请日:2018-10-24

    CPC classification number: G01R31/2834 G01R31/2872 G06F11/263 G06F21/73

    Abstract: Techniques regarding autonomous identification of aged circuits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an identification component, operatively coupled to the processor, that can identify an aged circuit by analyzing a current-voltage characteristic curve for a distortion in a sub-threshold quiescent current signature of the aged circuit.

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