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    RRAM filament spatial localization using a laser stimulation
    1.
    发明授权
    RRAM filament spatial localization using a laser stimulation 有权

    公开(公告)号：US11901002B2

    公开(公告)日：2024-02-13

    申请号：US17539295

    申请日：2021-12-01

    Applicant: International Business Machines Corporation

    Inventor： Franco Stellari ,  Ernest Y. Wu ,  Takashi Ando ,  Peilin Song

    IPC: G11C13/00 ,  H10N70/20 ,  H10N70/00

    CPC classification number: G11C13/0064 ,  G11C13/0007 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8833

    Abstract: System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

    Protecting Against Emission Based Side Channel Detection
    3.
    发明申请
    Protecting Against Emission Based Side Channel Detection 有权

    公开(公告)号：US20220366113A1

    公开(公告)日：2022-11-17

    申请号：US17319286

    申请日：2021-05-13

    Applicant: International Business Machines Corporation

    Inventor： Peilin Song ,  Franco Stellari ,  Gi-Joon Nam ,  Jinwook Jung ,  Victor N. Kravets ,  Jagannathan Narasimhan ,  Jennifer Kazda ,  Dirk Pfeiffer

    IPC: G06F30/337 ,  G06F30/327 ,  G06F30/3315 ,  G06F30/398

    Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

    Imaging integrated circuits using a single-point single-photon detector and a scanning system and calculating of a per-pixel value
    5.
    发明授权
    Imaging integrated circuits using a single-point single-photon detector and a scanning system and calculating of a per-pixel value 有权

    公开(公告)号：US11287630B2

    公开(公告)日：2022-03-29

    申请号：US16559594

    申请日：2019-09-03

    Applicant: International Business Machines Corporation

    Inventor： Franco Stellari ,  Peilin Song

    IPC: G02B21/00 ,  G01J3/443 ,  G01J1/44

    Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.

    TAMPER RESISTANT OBFUSCATION CIRCUIT
    6.
    发明申请
    TAMPER RESISTANT OBFUSCATION CIRCUIT 有权

    公开(公告)号：US20220019703A1

    公开(公告)日：2022-01-20

    申请号：US16933509

    申请日：2020-07-20

    Applicant: International Business Machines Corporation

    Inventor： Jean-Olivier Plouchart ,  Dirk Pfeiffer ,  Arvind Kumar ,  Takashi Ando ,  Peilin Song

    IPC: G06F21/86 ,  G06F21/14 ,  G06F21/79

    Abstract: An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

    Integrated circuit identification
    8.
    发明授权
    Integrated circuit identification 有权

    公开(公告)号：US11036832B2

    公开(公告)日：2021-06-15

    申请号：US16683368

    申请日：2019-11-14

    Applicant: International Business Machines Corporation

    Inventor： Andrea Bahgat Shehata ,  Peilin Song ,  Franco Stellari

    IPC: G06F21/14 ,  G06F30/398 ,  G06F30/00 ,  G06F30/30

    Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

    Method and system for quickly identifying circuit components in an emission image
    10.
    发明授权
    Method and system for quickly identifying circuit components in an emission image 有权

    公开(公告)号：US10895596B2

    公开(公告)日：2021-01-19

    申请号：US15412517

    申请日：2017-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Peilin Song ,  Franco Stellari

    IPC: G01R31/311 ,  G06T7/00 ,  G06T7/11 ,  G01R31/28

    Abstract: Methods and systems for localizing and resolving an integrated circuit include selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli provide a baseline image and a distinguishing image effect when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set and to collect the baseline image and the distinguishing image effect. The measurement includes dividing a field of view in a photon emission image into regions of interest. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect. The analysis includes calculating a figure of merit for each region of interest that represents a degree of switching activity in the respective region of interest.

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