公开(公告)号：US11194375B2

公开(公告)日：2021-12-07

申请号：US15836281

申请日：2017-12-08

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Abdul Ismail ,  Karthi Vadivelu ,  Yong Yang

IPC: G06F1/3215 ,  G06F13/38 ,  H04L12/40 ,  G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/26

Abstract: An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

公开(公告)号：US20210232454A1

公开(公告)日：2021-07-29

申请号：US17229162

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Andrew Martwick ,  Howard Heck ,  Robert Dunstan ,  Dennis Bell ,  Abdul Ismail

IPC: G06F11/10 ,  H03M5/06 ,  H03M5/12

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

公开(公告)号：US10997016B2

公开(公告)日：2021-05-04

申请号：US16506066

申请日：2019-07-09

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Andrew Martwick ,  Howard Heck ,  Robert Dunstan ,  Dennis Bell ,  Abdul Ismail

IPC: H03M5/06 ,  G06F11/10 ,  H03M5/12

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

公开(公告)号：US10025748B2

公开(公告)日：2018-07-17

申请号：US14040421

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Dennis M. Bell ,  Robert A. Dunstan ,  Duane G. Quiet ,  Gary A. Solomon

IPC: G06F13/36 ,  G06F13/42

Abstract: A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.

公开(公告)号：US20170262403A1

公开(公告)日：2017-09-14

申请号：US15607371

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4072 ,  G06F13/4295 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US20160191313A1

公开(公告)日：2016-06-30

申请号：US14582597

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Howard L. Heck

IPC: H04L12/24 ,  H04W52/28

CPC classification number: H04L41/0816 ,  H04L12/12

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract translation: 本文描述了重新定时器配置和控制的装置。 该装置包括至少一个重定时器。 接收带内低频周期信号（LFPS），并响应于带内LFPS发送基于带宽LFPS的脉宽调制消息（LBPM）。 重定时器通过对LBPM进行解码来配置。

公开(公告)号：US20160134415A1

公开(公告)日：2016-05-12

申请号：US14919024

申请日：2015-10-21

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Christopher Hull ,  Thomas A. Tetzlaff

IPC: H04L5/16

CPC classification number: H04L5/16 ,  H04L5/0053 ,  H04L5/14 ,  H04W84/12

Abstract: Embodiments of a multi-transceiver wireless communication device and methods for adaptive multi-band communication are generally described herein. In some embodiments, the multi-transceiver wireless communication device is configurable for half-duplex operation and for asymmetrical full-duplex operation on two non-interfering channels. In some embodiments, a contention-based channel access procedure may be performed to attempt to gain access to both a primary channel and an auxiliary channel. A primary transceiver and an auxiliary transceiver may be configured for asymmetrical full-duplex operation when access to both the primary channel and the auxiliary channel is granted. One of the transceivers may be configured for half-duplex operation when access to only one of the channels is granted. During asymmetrical full-duplex operation, the primary transceiver may be configured to communicate data packets using the primary channel, and the auxiliary transceiver may be configured to communicate control packets using an auxiliary channel.

Abstract translation: 多收发器无线通信装置的实施例和用于自适应多频带通信的方法在本文中一般地被描述。 在一些实施例中，多收发器无线通信设备可配置用于半双工操作和用于两个非干扰信道上的非对称全双工操作。 在一些实施例中，可以执行基于竞争的信道接入过程以试图获得对主信道和辅助信道的接入。 当允许访问主信道和辅助信道时，主收发机和辅助收发机可被配置用于不对称全双工操作。 其中一个收发器可以被配置为半双工操作，当仅允许访问仅一个信道时。 在非对称全双工操作期间，主收发器可以被配置为使用主信道传送数据分组，并且辅助收发机可以被配置为使用辅助信道来传送控制分组。