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    Digital interconnects with protocol-agnostic repeaters
    2.
    发明授权
    Digital interconnects with protocol-agnostic repeaters 有权

    公开(公告)号：US10108577B2

    公开(公告)日：2018-10-23

    申请号：US14672168

    申请日：2015-03-28

    Applicant: Intel Corporation

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS
    3.
    发明申请
    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS 审中-公开

    公开(公告)号：US20170262402A1

    公开(公告)日：2017-09-14

    申请号：US15607367

    申请日：2017-05-26

    Applicant: INTEL CORPORATION

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/42

    CPC classification number: G06F13/4291

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS
    4.
    发明申请
    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS 审中-公开

    公开(公告)号：US20170262401A1

    公开(公告)日：2017-09-14

    申请号：US15607362

    申请日：2017-05-26

    Applicant: INTEL CORPORATION

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  G06F13/4072 ,  G06F13/4295 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS
    5.
    发明申请
    DIGITAL INTERCONNECTS WITH PROTOCOL-AGNOSTIC REPEATERS 审中-公开
    与协议代理商的数字互联

    公开(公告)号：US20160196233A1

    公开(公告)日：2016-07-07

    申请号：US14672168

    申请日：2015-03-28

    Applicant: Intel Corporation

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/42 ,  H04L27/32

    CPC classification number: G06F13/4291

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    Abstract translation: 描述了一种系统和方法，用于简化在承载相对低数据速率时钟信号以及数据流（例如，数据速率）的高数据速率互连中的中继器（例如，重新驱动/重新定时器）模块的实现。 ，PCIe）。 在端点处，对于中继器功能至关重要的任何信息（例如，通过中继器通信的一对端点协商的最新数据速率）通过脉冲宽度调制作为有序集合被嵌入到时钟信号中。 中继器只需要读取时钟嵌入信息，而不是解码数据流。 因此，用于这种应用的中继器重建高速率数据流，同时仅实现仅解码低速率时钟信号。 由于时钟信号协议独立于数据流协议，所以中继器的操作与数据流相比是协议无关的。

    Digital interconnects with protocol-agnostic repeaters
    6.
    发明授权
    Digital interconnects with protocol-agnostic repeaters 有权

    公开(公告)号：US10235327B2

    公开(公告)日：2019-03-19

    申请号：US15607371

    申请日：2017-05-26

    Applicant: INTEL CORPORATION

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    Digital interconnects with protocol-agnostic repeaters
    7.
    发明授权
    Digital interconnects with protocol-agnostic repeaters 有权

    公开(公告)号：US10223324B2

    公开(公告)日：2019-03-05

    申请号：US15607362

    申请日：2017-05-26

    Applicant: INTEL CORPORATION

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

    Out-of band interrupt mapping in MIPI improved inter-integrated circuit communication
    8.
    发明授权
    Out-of band interrupt mapping in MIPI improved inter-integrated circuit communication 有权

    公开(公告)号：US10769084B2

    公开(公告)日：2020-09-08

    申请号：US15474117

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Kenneth P. Foust ,  Duane G. Quiet ,  Amit Kumar Srivastava

    IPC: G06F13/24 ,  G06F13/42

    Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

    Digital interconnects with protocol-agnostic repeaters
    9.
    发明授权
    Digital interconnects with protocol-agnostic repeaters 有权

    公开(公告)号：US10127187B2

    公开(公告)日：2018-11-13

    申请号：US15607367

    申请日：2017-05-26

    Applicant: INTEL CORPORATION

    Inventor： Huimin Chen ,  Duane G. Quiet

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

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