公开(公告)号：US11119704B2

公开(公告)日：2021-09-14

申请号：US16367608

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/54

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

公开(公告)号：US20160283425A1

公开(公告)日：2016-09-29

申请号：US14671465

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Nitin V. Sarangdhar ,  Steven B. McGowan ,  Raul Gutierrez ,  Karthi R. Vadivelu

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F13/4282

Abstract: An apparatus is described herein. The apparatus includes a Universal Serial Bus (USB) component and a controller interface. The controller interface is to allocate register space for interfacing with the USB component and the USB component is virtualized into multiple instantiations. The apparatus also includes a secure environment, and the secure environment further virtualizes the multiple instantiations such that the multiple instantiations are owned by the secure environment.

Abstract translation: 这里描述了一种装置。 该装置包括通用串行总线（USB）组件和控制器接口。 控制器接口是分配与USB组件接口的寄存器空间，并将USB组件虚拟化为多个实例。 该装置还包括安全环境，并且安全环境进一步虚拟化多个实例，使得多个实例由安全环境所拥有。

公开(公告)号：US20160191313A1

公开(公告)日：2016-06-30

申请号：US14582597

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Howard L. Heck

IPC: H04L12/24 ,  H04W52/28

CPC classification number: H04L41/0816 ,  H04L12/12

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract translation: 本文描述了重新定时器配置和控制的装置。 该装置包括至少一个重定时器。 接收带内低频周期信号（LFPS），并响应于带内LFPS发送基于带宽LFPS的脉宽调制消息（LBPM）。 重定时器通过对LBPM进行解码来配置。

公开(公告)号：US20150212969A1

公开(公告)日：2015-07-30

申请号：US14678712

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Karthi R. Vadivelu ,  SRIDHARAN RANGANATHAN ,  ANOOP MUKKER ,  SATHEESH CHELLAPPAN

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F13/426 ,  G06F13/122 ,  G06F13/126 ,  G06F13/387 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract translation: 用于本文提供的设备中的单元之间的低功率，高带宽通信的接口。 该接口包括USB 3.0系统接口和配置为促进USB3.0系统接口和M-PHY接口之间的通信的SuperSpeed芯片间（SSIC）协议适配器，其中SSIC配置为发出远程注册访问协议（RRAP ）通过本地M-PHY以低速突发模式命令到远程M-PHY。

公开(公告)号：US11263165B2

公开(公告)日：2022-03-01

申请号：US15396573

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Karthi R. Vadivelu ,  Abdul R. Ismail ,  Nausheen Ansari

IPC: G06F13/42 ,  G06F13/40

Abstract: Apparatuses relating to periodic Universal Serial Bus (USB) transaction scheduling at fractional bus intervals are described. In one embodiment, an apparatus includes a receptacle to receive a plug of a first device and a second device; a transceiver circuit coupled to the receptacle; and a controller circuit to: switch between a first mode for a first class of data transfers and a second mode for a second class of data transfers, wherein the first class preempts the second class of data transfers, schedule a data transfer with the transceiver circuit for a first endpoint of the first device at a first service interval of a bus interval when in the first mode, and schedule a data transfer with the transceiver circuit for a second, different endpoint of the second device at a second service interval that is smaller than the first service interval when in the first mode.

公开(公告)号：US20190042483A1

公开(公告)日：2019-02-07

申请号：US15941273

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Darren Abramson ,  David Hines ,  Alberto Martinez ,  Adeel Aslam ,  John Howard ,  Shanthanand R. Kutuva ,  Karthi R. Vadivelu ,  Kar Leong Wong ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/38

CPC classification number: G06F13/102 ,  G06F13/385 ,  G06F2209/509 ,  G06F2213/0042

Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

公开(公告)号：US20180046522A1

公开(公告)日：2018-02-15

申请号：US15558116

申请日：2016-03-21

Applicant: Intel Corporation

Inventor： Peter S. Adamson ,  Nivedita Aggarwal ,  Karunakara Kotary ,  Abdul Rahman Ismail ,  Tin-Cheung Kung ,  David T. Hines ,  Chia-Hung Sophia Kuo ,  Ajay V. Bhatt ,  Karthi R. Vadivelu ,  Prashant Sethi

IPC: G06F9/54

Abstract: Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local policy manager, where the local policy manager is in communication with the multimodal interface. The multimodal interface can be configured to support power transfers, directionality, and multiple input/output (I/O) protocols on the same interface.

公开(公告)号：US09559905B2

公开(公告)日：2017-01-31

申请号：US14582597

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Howard L. Heck

IPC: H04L12/24 ,  H04W52/28 ,  H04L12/12

CPC classification number: H04L41/0816 ,  H04L12/12

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract translation: 本文描述了重新定时器配置和控制的装置。 该装置包括至少一个重定时器。 接收带内低频周期信号（LFPS），并响应于带内LFPS发送基于带宽LFPS的脉宽调制消息（LBPM）。 重定时器通过对LBPM进行解码来配置。

公开(公告)号：US11281597B2

公开(公告)日：2022-03-22

申请号：US15792538

申请日：2017-10-24

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Abdul R. Ismail ,  Raul Gutierrez

IPC: G06F13/10 ,  G06F13/28 ,  G06F13/40 ,  H04N5/232 ,  H04N7/14 ,  G06F13/38 ,  H04N7/18 ,  G06F13/42

Abstract: Embodiments of the present disclosure are directed toward a universal serial bus (USB) device and a USB host controller. The USB device and USB host controller may be configured to couple to one another via a USB link that may include a high-speed data line and a low-speed data line. The USB device may then transmit, via the high-speed data line, an indication of a digital image to the USB host controller. Other embodiments may be described and/or claimed.

公开(公告)号：US09904650B2

公开(公告)日：2018-02-27

申请号：US14678712

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Karthi R. Vadivelu ,  Sridharan Ranganathan ,  Anoop Mukker ,  Satheesh Chellappan

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F13/426 ,  G06F13/122 ,  G06F13/126 ,  G06F13/387 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.