公开(公告)号：US20200074714A1

公开(公告)日：2020-03-05

申请号：US16566989

申请日：2019-09-11

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/00 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US10553019B2

公开(公告)日：2020-02-04

申请号：US15398111

申请日：2017-01-04

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth

IPC: G06T15/50 ,  G06T1/20

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

公开(公告)号：US10430189B2

公开(公告)日：2019-10-01

申请号：US15709213

申请日：2017-09-19

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Tomasz Janczak ,  Travis Schluessler ,  Subramaniam Maiyuran

IPC: G06F9/30 ,  G06F9/48 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus to facilitate register allocation is disclosed. The apparatus includes an execution unit (EU) to execute processing threads. The EU includes a plurality of registers and register allocation logic to map the plurality of registers into logical register banks and allocate the processing threads to one or more of the logical register banks.

公开(公告)号：US10417734B2

公开(公告)日：2019-09-17

申请号：US15698217

申请日：2017-09-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US10354434B1

公开(公告)日：2019-07-16

申请号：US16295234

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： David Baldwin ,  Karthik Vaidyanathan

IPC: G09G5/00 ,  G06T15/06 ,  G06T15/00

Abstract: A level of detail node may hold in a bounding volume hierarchy, an object identifier, a distance at which a transition occurs between levels of detail and a bias. When a level of detail node is encountered in the hierarchy, the distance value may be used to select a level of detail. Sometimes a different level of detail is loaded because the preferred level is not available. The different level may be marked in a register. Then for a subsequence frame, the correct level is used. A node bias may be used to override the level of detail selection is some cases.

公开(公告)号：US10311629B2

公开(公告)日：2019-06-04

申请号：US15004191

申请日：2016-01-22

Applicant: Intel Corporation

Inventor： David Baldwin ,  Karthik Vaidyanathan

IPC: G06T15/00 ,  G06T15/06

Abstract: A level of detail node may hold in a bounding volume hierarchy, an object identifier, a distance at which a transition occurs between levels of detail and a bias. When a level of detail node is encountered in the hierarchy, the distance value may be used to select a level of detail. Sometimes a different level of detail is loaded because the preferred level is not available. The different level may be marked in a register. Then for a subsequence frame, the correct level is used. A node bias may be used to override the level of detail selection is some cases.

公开(公告)号：US20180300944A1

公开(公告)日：2018-10-18

申请号：US15488641

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/80 ,  G06T17/20 ,  G06T7/13 ,  G06T7/136 ,  G06T15/00

CPC classification number: G06T15/503 ,  G06T7/13 ,  G06T7/136 ,  G06T15/005

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20180293703A1

公开(公告)日：2018-10-11

申请号：US15483829

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T1/60 ,  G06T9/00

Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286106A1

公开(公告)日：2018-10-04

申请号：US15477028

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/20 ,  G06T15/00 ,  G06T7/50 ,  G06T7/70 ,  G06T1/20 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US20170287100A1

公开(公告)日：2017-10-05

申请号：US15157667

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan

IPC: G06T1/20 ,  G06F12/08 ,  G06T15/06

CPC classification number: G06T1/20 ,  G06F12/0871 ,  G06F2212/1016 ,  G06F2212/302 ,  G06F2212/401 ,  G06T15/06 ,  G06T17/005

Abstract: Incremental encoding of Bounding Volume Hierarchies (BVH) enables coarse quantization of bounding volumes, significantly reducing their memory footprint. However, reducing the size of the BVH alone does not yield a comparable reduction in memory bandwidth in some embodiments. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. A two-level clustering method introduces a memory layout and node addressing scheme, which allows the reordering of BVH nodes to reduce their memory footprint in hardware ray tracing systems using reduced precision ray traversal.