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    Techniques to enforce policies for computing platform resources
    53.
    发明授权
    Techniques to enforce policies for computing platform resources 有权

    公开(公告)号：US11876835B2

    公开(公告)日：2024-01-16

    申请号：US17502787

    申请日：2021-10-15

    Applicant: INTEL CORPORATION

    Inventor： Siddhartha Chhabra ,  Prashant Dewan

    IPC: H04L9/40 ,  H04L9/32 ,  G06F9/30 ,  G06F21/57 ,  G06F21/62 ,  G06F21/74

    CPC classification number: H04L63/20 ,  G06F9/30101 ,  G06F21/57 ,  G06F21/62 ,  G06F21/74 ,  H04L9/3242 ,  H04L63/105 ,  H04L63/1458 ,  H04L2209/12

    Abstract: Various embodiments are generally directed to techniques to enforce policies for computing platform resources, such as to prevent denial of service (DoS) attacks on the computing platform resources. Some embodiments are particularly directed to ISA instructions that allow trusted software/applications to securely enforce policies on a platform resource/device while allowing untrusted software to control allocation of the platform resource. In many embodiments, the ISA instructions may enable secure communication between a trusted application and a platform resource. In several embodiments, a first ISA instruction implemented by microcode may enable a trusted application to wrap policy information for secure transmission through an untrusted stack. In several such embodiments, a second ISA instruction implemented by microcode may enable untrusted software to verify the validity of the wrapped blobs and program registers associated with the platform resource with policy information provided via the wrapped blobs.

    Apparatus and method for secure, efficient microcode patching
    55.
    发明授权
    Apparatus and method for secure, efficient microcode patching 有权

    公开(公告)号：US11720363B2

    公开(公告)日：2023-08-08

    申请号：US17485400

    申请日：2021-09-25

    Applicant: Intel Corporation

    Inventor： Prashant Dewan ,  Arun Hodigere ,  Karunakara Karunakara Kotary

    IPC: G06F9/30 ,  G06F12/02 ,  G06F9/26

    CPC classification number: G06F9/30145 ,  G06F9/268 ,  G06F9/3017 ,  G06F12/0246

    Abstract: An apparatus and method for efficient microcode patching. For example, one embodiment of an apparatus comprises: a package comprising one or more integrated circuit dies, the one or more integrated circuit dies comprising: a plurality of cores; and a security controller coupled to the plurality of cores, a first core of the plurality of cores comprising: a decoder to decode a microcode patching instruction, the microcode patching instruction comprising an operand to be used to identify an address; and execution circuitry to execute the microcode patching instruction, wherein responsive to the microcode patching instruction, the execution circuitry and/or security controller are to: retrieve a microcode patch from a location in memory based on the address, validate the microcode patch, apply the microcode patch to update or replace microcode associated with the one or more integrated circuit dies, and transmit the microcode patch to a persistent storage device; wherein the microcode patch is to be subsequently retrieved from the persistent storage device by one or more external security controllers of one or more external integrated circuit dies, the one or more external security controllers to cause the microcode patch to be applied to update or replace microcode associated with the one or more external integrated circuit dies.

    SECURING DATA DIRECT I/O FOR A SECURE ACCELERATOR INTERFACE
    56.
    发明申请
    SECURING DATA DIRECT I/O FOR A SECURE ACCELERATOR INTERFACE 有权

    公开(公告)号：US20230032740A1

    公开(公告)日：2023-02-02

    申请号：US17946762

    申请日：2022-09-16

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Abhishek Basak ,  David M. Durham

    IPC: G06F12/14 ,  G06F12/0831 ,  G06F13/28 ,  G06F21/78 ,  G06F21/85 ,  G06F21/60

    Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modem data central processor units (CPUs).

    ISA accessible physical unclonable function
    57.
    发明授权
    ISA accessible physical unclonable function 有权

    公开(公告)号：US11570010B2

    公开(公告)日：2023-01-31

    申请号：US17134365

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Baiju Patel

    IPC: H04L9/32 ,  G06F9/30 ,  H04L9/08

    Abstract: Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.

    Securing data direct I/O for a secure accelerator interface
    60.
    发明授权
    Securing data direct I/O for a secure accelerator interface 有权

    公开(公告)号：US11481337B2

    公开(公告)日：2022-10-25

    申请号：US17022029

    申请日：2020-09-15

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Abhishek Basak ,  David M. Durham

    IPC: G06F21/60 ,  G06F12/14 ,  G06F12/0831 ,  G06F21/78 ,  G06F13/28 ,  G06F21/85

    Abstract: The present disclosure includes systems and methods for securing data direct I/O (DDIO) for a secure accelerator interface, in accordance with various embodiments. Historically, DDIO has enabled performance advantages that have outweighed its security risks. DDIO circuitry may be configured to secure DDIO data by using encryption circuitry that is manufactured for use in communications with main memory along the direct memory access (DMA) path. DDIO circuitry may be configured to secure DDIO data by using DDIO encryption circuitry manufactured for use by or manufactured within the DDIO circuitry. Enabling encryption and decryption in the DDIO path by the DDIO circuitry has the potential to close a security gap in modern data central processor units (CPUs).

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