公开(公告)号：US20170160987A1

公开(公告)日：2017-06-08

申请号：US14961937

申请日：2015-12-08

Applicant: Intel Corporation

Inventor： Robert J. Royer, JR. ,  Blaise Fanning

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/08 ,  G06F2212/1024 ,  G06F2212/466 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7211

Abstract: The present disclosure relates to a memory system with main memory. The main memory includes first level main memory and second level main memory. The first level main memory is configured to store indirection information providing reference to physical memory units of the second level main memory. Further, the memory system includes a memory controller configured to initiate an access of a physical memory unit of the second level main memory using the indirection information stored in the first level main memory.

公开(公告)号：US20170337103A1

公开(公告)日：2017-11-23

申请号：US15159700

申请日：2016-05-19

Applicant: Intel Corporation

Inventor： Robert J. Royer, JR.

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1088

Abstract: A solid-state drive may be coupled via an interface with a processing device that receives an indication of a failure of a logical unit of a non-volatile memory of the solid-state drive. In response to the indication of the failure, parity data at locations of other logical units of the non-volatile memory of the solid-state drive may be identified. User data from the logical unit may be reconstructed based on the parity data from the locations of the other logical units of the non-volatile memory of the solid-state drive. Furthermore, the reconstructed user data from the logical unit may be stored at the locations of the other logical units that store the parity data.

公开(公告)号：US20220416997A1

公开(公告)日：2022-12-29

申请号：US17357973

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prashant Dewan ,  Siddhartha Chhabra ,  Robert J. Royer, JR. ,  Michael Glik ,  Baiju Patel

IPC: H04L9/06 ,  G06F21/72

Abstract: Methods and apparatus relating to handling unaligned transactions for inline encryption are described. In an embodiment, cryptographic logic circuitry receives a plurality of incoming packets and store two or more incoming packets from the plurality of incoming packets in memory. The cryptographic logic circuitry is informs software in response to detection of the two or more incoming packets. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170024138A1

公开(公告)日：2017-01-26

申请号：US15132154

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Robert J. Royer, JR.

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了管理存储器操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和存储器控制逻辑以从存储器设备检索全局序列号，接收对存储在存储器设备中的逻辑块地址中的数据的读取请求，从存储器设备中检索媒体序列号 逻辑块地址，并且当媒体序列号比全局序列号更早时，返回空响应代替存储在逻辑块地址中的数据。 还公开并要求保护其他实施例。

公开(公告)号：US20140223231A1

公开(公告)日：2014-08-07

申请号：US13976002

申请日：2012-06-07

Applicant: INTEL CORPORATION

Inventor： Richard P. Mangold ,  Richard L. Coulson ,  Robert J. Royer, JR. ,  Sanjeev N. Trika

IPC: G06F11/07 ,  G11C16/16 ,  G06F3/06

CPC classification number: G11C16/16

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在功率损耗恢复中用于固态驱动器管理的设备，方法，计算机可读介质和系统配置。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190129792A1

公开(公告)日：2019-05-02

申请号：US15756039

申请日：2018-02-27

Applicant: Intel Corporation

Inventor： Robert J. Royer, JR. ,  Blaise Fanning ,  Eng Hun Ooi

IPC: G06F11/10 ,  G06F12/0866

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.