公开(公告)号：US10256972B2

公开(公告)日：2019-04-09

申请号：US14984629

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10256971B2

公开(公告)日：2019-04-09

申请号：US14984601

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US09906359B2

公开(公告)日：2018-02-27

申请号：US15405898

申请日：2017-01-13

Applicant: Intel Corporation

Inventor： Shay Gueron

IPC: G06F9/30 ,  H04L9/06 ,  G06F7/00 ,  G06F21/60 ,  G06F9/38

CPC classification number: H04L9/0631 ,  G06F7/00 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3887 ,  G06F21/602 ,  H04L2209/34

Abstract: Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

公开(公告)号：US20170337145A1

公开(公告)日：2017-11-23

申请号：US15612845

申请日：2017-06-02

Applicant: INTEL CORPORATION

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

IPC: G06F13/24 ,  G06F12/0806 ,  G06F21/00 ,  G06F21/85 ,  G06F12/08 ,  G06F21/71 ,  G06F12/0875

CPC classification number: G06F13/24 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/62

Abstract: Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.

公开(公告)号：US20170310471A1

公开(公告)日：2017-10-26

申请号：US15639999

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US20170310469A1

公开(公告)日：2017-10-26

申请号：US15639983

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US20170310467A1

公开(公告)日：2017-10-26

申请号：US15639969

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US20170310465A1

公开(公告)日：2017-10-26

申请号：US15639946

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US09703733B2

公开(公告)日：2017-07-11

申请号：US14318508

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Gilbert Neiger ,  Francis X. McKeen ,  Ittai Anati ,  Vedvyas Shanbhogue ,  Shay Gueron

IPC: G06F12/00 ,  G06F13/24 ,  G06F12/0806 ,  G06F12/08 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85

CPC classification number: G06F13/24 ,  G06F12/08 ,  G06F12/0806 ,  G06F12/0875 ,  G06F21/00 ,  G06F21/71 ,  G06F21/85 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/62

Abstract: Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.

公开(公告)号：US20170195116A1

公开(公告)日：2017-07-06

申请号：US14569428

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Shay Gueron ,  Ram Krishnamurthy ,  Sanu K. Mathew

IPC: H04L9/06 ,  G06F9/38 ,  G06F21/60 ,  G06F9/30

CPC classification number: H04L9/0631 ,  G06F7/00 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3887 ,  G06F21/602 ,  H04L2209/34

Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.