公开(公告)号：US20100078790A1

公开(公告)日：2010-04-01

申请号：US12466018

申请日：2009-05-14

申请人： Kiyoto ITO ,  Makoto Saen ,  Yuki Kuroda

发明人： Kiyoto ITO ,  Makoto Saen ,  Yuki Kuroda

IPC分类号： H01L25/16 ,  H01L23/538

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H01L23/544 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.

摘要翻译： 在堆叠多个存储器LSI和多个处理器LSI的半导体器件中，随着堆叠层数的增加，存储器LSI和处理器LSI之间的数据的通信距离将增加。 因此，用于通信的布线的寄生电容和寄生电阻增加，结果整个系统的功率和速度性能将降低。 堆叠处理器LSI 100和存储器LSI 200的组合中的至少两个或更多个，并且相同组合的处理器LSI 100和存储器LSI 200在垂直方向上彼此相邻堆叠。 通过设置在其间的专用电极来执行处理器LSI 100和存储器LSI 200之间的相同组合的通信，并且处理器LSI 100之间的通信以及从处理器LSI 100到外部的通信由用于信号11的贯穿硅通道 通过所有的LSI。

公开(公告)号：US20100078635A1

公开(公告)日：2010-04-01

申请号：US12465819

申请日：2009-05-14

申请人： Yuki Kuroda ,  Makoto Saen ,  Hiroyuki Mizuno ,  Kiyoto Ito

发明人： Yuki Kuroda ,  Makoto Saen ,  Hiroyuki Mizuno ,  Kiyoto Ito

IPC分类号： H01L23/58 ,  H01L21/50

CPC分类号： H01L25/18 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014

摘要： As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories.

摘要翻译： 随着处理器LSI和存储器之间的转移逐年增加，需要增加通信量并降低通信所需的功率。 由于这是条件，因此考虑了堆叠LSI从而减少通信距离的方法。 然而，本发明人已经发现，对于处理器LSI和存储器LSI的简单堆叠，需要堆叠处理中的成本的降低和要堆叠的存储器LSI的选择的自由度的增加。 一种外部通信LSI，包括用于以高于1GHz的高速率与堆叠的LSI的外部进行通信的电路; 包括通用CPU等的处理器LSI; 并且依次堆叠包括DRAM等的存储器LSI，并且这些LSI通过硅通孔彼此连接，以使得能够以最短路径进行高速和高容量的通信。 此外，用于促进与处理器LSI的连接的插入器连接到要堆叠的存储器LSI的输入端，从而增加选择存储器的自由度。

公开(公告)号：US07337251B2

公开(公告)日：2008-02-26

申请号：US11304567

申请日：2005-12-16

申请人： Makoto Saen ,  Hiroshi Ueda ,  Eiji Yamamoto

发明人： Makoto Saen ,  Hiroshi Ueda ,  Eiji Yamamoto

IPC分类号： G06F13/18

CPC分类号： G06F13/1605 ,  G06F13/362

摘要： The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.

摘要翻译： 信息处理设备包括第一和第二主电路以及用于仲裁与主电路连接的总线的访问权限的仲裁器。 仲裁器具有保存表示访问权限优先级的信息的存储单元，以及用于基于该信息来仲裁主电路的访问权限的仲裁控制逻辑单元。 当第一主电路的优先级高于第二主电路的优先级，并且没有来自第一主电路的访问请求，但是存在来自第二主电路的访问请求时，仲裁控制逻辑单元允许访问 第二主电路，并且存储单元降低第二主电路的优先级，而不改变第一主电路的优先级。

公开(公告)号：US20070260791A1

公开(公告)日：2007-11-08

申请号：US11822966

申请日：2007-07-11

申请人： Makoto Saen ,  Kei Suzuki

发明人： Makoto Saen ,  Kei Suzuki

IPC分类号： G06F13/20

CPC分类号： G06F13/364

摘要： A data processing device which, even if congestion occurs on a bus circuit of a specific processing circuit in an LSI in which multiple circuit modules are connected by buses, can fully actualize the performance potential of the system on chip. Buses and slave circuits on which accesses concentrate are provided with observation blocks. Each observation block has a mechanism to notify system control circuits such as a clock controller and master circuits such as CPU cores of the acquired status information, and each master circuit further has a mechanism capable of dynamically altering the priority order for notifying the bus circuits and slave circuits of the priority order of processing.

摘要翻译： 一种数据处理装置，即使在通过总线连接多个电路模块的LSI中的特定处理电路的总线电路上发生拥塞，也能够充分实现片上系统的性能潜力。 带有观察块的访问集中的巴士和从属电路。 每个观测块具有通知诸如时钟控制器和所获取的状态信息的CPU核心的主电路的系统控制电路的机制，并且每个主电路还具有能够动态地改变用于通知总线电路的优先级顺序的机构， 从电路处理的优先级顺序。