公开(公告)号：US20100103713A1

公开(公告)日：2010-04-29

申请号：US12532914

申请日：2008-03-27

申请人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

发明人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

IPC分类号： G11C5/02 ,  G11C7/00

CPC分类号： G06F13/4239 ,  G11C5/02 ,  G11C5/04 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/10159 ,  Y02P70/611

摘要： A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.

摘要翻译： 存储器系统包括电路板40，其包括N条数据信号线60,65和至少两个选通信号线70,75以及固定到电路板的相对表面40a，40b的第一和第二存储器件50,55。 每个存储器件耦合到N个数据信号线的一部分和至少两个选通信号线的一部分，使得器件不共享N个数据信号线中的任何一个，并且使得器件不共享 选通信号线。 存储系统还包括控制器45，通过N个数据信号线和至少两个选通信号线与第一和第二存储器装置并行通信。

公开(公告)号：US20100008414A1

公开(公告)日：2010-01-14

申请号：US12522362

申请日：2008-01-07

申请人： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

发明人： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC分类号： H04L27/01

CPC分类号： H04L25/03159 ,  H04B1/123 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03636

摘要： A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

摘要翻译： 接收机包括连续时间均衡器，判决反馈均衡器（DFE），数据和误差采样逻辑以及适配引擎。 接收机通过基于第一后视标ISI的测量建立连续时间均衡器的适当均衡设置来校正与最新数据符号（第一后光标ISI）相关联的符号间干扰（ISI）。

公开(公告)号：US07543172B2

公开(公告)日：2009-06-02

申请号：US11019432

申请日：2004-12-21

申请人： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

发明人： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC分类号： G06F1/12

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

摘要： Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components of a host system use the masked strobe signal to receive or transfer data from the clock domain of the strobe signal through a mesochronous clock domain crossing into a different clock domain.

摘要翻译： 以下提供了用于屏蔽基于选通信号的系统中的选通信号的系统和方法。 这些选通屏蔽系统从在一个时钟域下操作的组件接收选通信号，并且产生选通信号的屏蔽版本。 主机系统的组件使用屏蔽的选通信号通过穿过不同时钟域的中间时钟域从选通信号的时钟域接收或传输数据。

公开(公告)号：US07246274B2

公开(公告)日：2007-07-17

申请号：US10939028

申请日：2004-09-10

申请人： Jade M. Kizer ,  Christopher J. Madden

发明人： Jade M. Kizer ,  Christopher J. Madden

IPC分类号： G06F11/00

CPC分类号： G06F11/004 ,  G01R31/31709 ,  G01R31/3171 ,  G11C29/022

摘要： An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.

摘要翻译： 一种装置和方法提供了对诸如处理器和存储器装置的IC之间的接口的BER的预测，而不使用特殊的测试设备。 已知的数据模式或PRBS被发送到接收机，接收机将接收到的数据值与期望的数据值进行比较，以确定在本发明的实施例中是否发生了位错误。 数据眼的中心和数据眼的边缘被采样（过采样），以便确定在本发明的替代实施例中是否发生位错误。 第一计数器用于对采样的总位数进行计数，第二计数器用于对所采样总位数中发生的错误数进行计数。

公开(公告)号：US07072355B2

公开(公告)日：2006-07-04

申请号：US10645201

申请日：2003-08-21

申请人： Jade M. Kizer

发明人： Jade M. Kizer

IPC分类号： H04L12/66

CPC分类号： H03M9/00 ,  H04L7/0008 ,  H04L7/043 ,  H04L7/10 ,  H04L25/14

摘要： A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with communications on N of the N+1 communication lines.