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    Partial response decision-feedback equalization with adaptation based on edge samples
    6.
    发明授权
    Partial response decision-feedback equalization with adaptation based on edge samples 有权
    基于边缘样本的部分响应决策反馈均衡与适应

    公开(公告)号：US08477834B2

    公开(公告)日：2013-07-02

    申请号：US12513898

    申请日：2007-11-09

    申请人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    发明人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC分类号： H03H7/30 ,  H04L27/06 ,  H04B1/10

    CPC分类号： H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    摘要： A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

    摘要翻译： 设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。 在一个示例性实施例中，该装置实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。 抽头重量适配器电路（119）基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。 时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

    Signaling with Superimposed Differential-Mode and Common-Mode Signals
    9.
    发明申请
    Signaling with Superimposed Differential-Mode and Common-Mode Signals 有权
    信号与叠加的差分模式和共模信号

    公开(公告)号：US20100272215A1

    公开(公告)日：2010-10-28

    申请号：US12739938

    申请日：2008-10-28

    申请人： Qi Lin ,  Hae-Chang Lee ,  Jacha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

    发明人： Qi Lin ,  Hae-Chang Lee ,  Jacha Kim ,  Brian S. Leibowitz ,  Jared L. Zerbe ,  Jihong Ren

    IPC分类号： H04L27/00

    CPC分类号： H04L25/0272 ,  H04L5/20 ,  H04L25/0262

    摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,—the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

    摘要翻译： 数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。 第一和第二相应的传输线包括数据接收器电路外部的一对传输线。 第一和第二接口从一对传输线接收传输信号。 共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。 差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。 所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。 差分模式电路与提取的时钟信号同步。