利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

92 条记录 (耗时 0.027 秒)

    IDENTIFICATION OF QOS CLASSIFICATION BASED ON PACKET ATTRIBUTES
    51.
    发明申请
    IDENTIFICATION OF QOS CLASSIFICATION BASED ON PACKET ATTRIBUTES 有权
    基于分组属性的QOS分类识别

    公开(公告)号：US20120300630A1

    公开(公告)日：2012-11-29

    申请号：US13302489

    申请日：2011-11-22

    申请人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin B. Verrilli

    发明人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin B. Verrilli

    IPC分类号： H04L12/24

    CPC分类号： H04L47/2441 ,  H04L69/22

    摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.

    摘要翻译： 公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。 该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

    Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information
    53.
    发明授权
    Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information 有权
    基于广播信息将作业动态地分配给集群中的处理器的技术

    公开(公告)号：US08122132B2

    公开(公告)日：2012-02-21

    申请号：US12336312

    申请日：2008-12-16

    申请人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

    发明人： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

    IPC分类号： G06F13/00

    CPC分类号： G06F9/5088

    摘要： A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).

    摘要翻译： 用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息 多个节点中的一个。 基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。 然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

    Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters
    54.
    发明授权
    Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters 有权
    访问有效地址并确定有效地址是否与远程耦合的I / O适配器相关联

    公开(公告)号：US07844746B2

    公开(公告)日：2010-11-30

    申请号：US12024695

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Edward J. Seminaro

    发明人： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Edward J. Seminaro

    IPC分类号： G06F3/12

    CPC分类号： G06F9/45558 ,  G06F2009/45579

    摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.

    摘要翻译： 提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。 为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于 例。 异构处理元件模型抽象出I / O设备，使得针对I / O设备的通信可以被分组并通过网络发送。 因此，虚拟化平台可以打包用于远程位置的I / O设备的通信，并且在一定距离上发送分组化的通信，而不是必须对库进行呼叫，调用设备驱动器，引脚存储器等。

    Oversubscribing Bandwidth In A Communications Network
    57.
    发明申请
    Oversubscribing Bandwidth In A Communications Network 有权
    在通信网络中超频带宽

    公开(公告)号：US20090097404A1

    公开(公告)日：2009-04-16

    申请号：US12272711

    申请日：2008-11-17

    申请人： Philippe Damon ,  Claude Basso ,  Jean L. Calvignac ,  Francis Arts ,  Pierre L. Debuysscher

    发明人： Philippe Damon ,  Claude Basso ,  Jean L. Calvignac ,  Francis Arts ,  Pierre L. Debuysscher

    IPC分类号： H04L12/24 ,  G01R31/08

    CPC分类号： H04L47/10 ,  H04L47/20

    摘要： A system and computer readable medium for oversubscribing bandwidth in a communication network, is disclosed. The system and computer readable medium includes policing a first data flow and outputting a first output data flow from the first meter, in relation to a first Committed Information Rate (CIR) and a first Peak Information Rate (PIR); policing a second data flow and outputting a second output data flow from the second meter in relation to a second CIR and a second PIR; and policing an aggregated output data flow of the first output data flow and the second output data through a third meter of the oversubscription module, where the aggregated output data flow is policed in relation to a third CIR and a third PIR.

    摘要翻译： 公开了一种在通信网络中超额订购带宽的系统和计算机可读介质。 系统和计算机可读介质包括对第一数据流进行管理，并相对于第一承诺信息速率（CIR）和第一峰值信息速率（PIR）从第一仪表输出第一输出数据流; 管理第二数据流，并相对于第二CIR和第二PIR从第二计量器输出第二输出数据流; 以及通过所述超额预订模块的第三计量管理所述第一输出数据流和所述第二输出数据的聚合输出数据流，其中所述聚合输出数据流相对于第三CIR和第三PIR进行监管。

    Network data packet processing
    58.
    发明授权
    Network data packet processing 有权
    网络数据包处理

    公开(公告)号：US08959224B2

    公开(公告)日：2015-02-17

    申请号：US13299045

    申请日：2011-11-17

    申请人： Claude Basso ,  Jean L. Calvignac ,  Hubertus Franke ,  Eren Kursun

    发明人： Claude Basso ,  Jean L. Calvignac ,  Hubertus Franke ,  Eren Kursun

    IPC分类号： G06F15/173 ,  G06F9/46 ,  G06F1/32 ,  G06F9/50

    CPC分类号： G06F1/3209 ,  G06F9/5094 ,  Y02D10/22

    摘要： A method and apparatus for processing of data packets by a data processing component comprising a plurality of processing resources. A metric value for a current configuration of the processing resources that are processing the data packets is identified. A new configuration of the processing resources is selected using the metric value. The current configuration of the processing resources is changed to the new configuration and data packets are distributed to the new configuration for processing as the data packets are received.

    摘要翻译： 一种由包括多个处理资源的数据处理组件处理数据分组的方法和装置。 识别处理数据分组的处理资源的当前配置的度量值。 使用度量值选择处理资源的新配置。 处理资源的当前配置被改变为新的配置，并且数据分组被分配到新配置，以便在接收到数据分组时进行处理。

    Assigning work from multiple sources to multiple sinks given assignment constraints
    59.
    发明授权
    Assigning work from multiple sources to multiple sinks given assignment constraints 失效
    给定分配约束将工作从多个源分配给多个汇点

    公开(公告)号：US08532129B2

    公开(公告)日：2013-09-10

    申请号：US12650120

    申请日：2009-12-30

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/28

    CPC分类号： H04L49/9047

    摘要： Assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device is provided. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

    摘要翻译： 提供了诸如数据分组的工作，诸如诸如网络处理设备中的数据队列的多个源到网络处理设备中的诸如处理器线程的多个接收器。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

    Supporting multiple high bandwidth I/O controllers on a single chip
    60.
    发明授权
    Supporting multiple high bandwidth I/O controllers on a single chip 有权
    在单个芯片上支持多个高带宽I / O控制器

    公开(公告)号：US08332552B2

    公开(公告)日：2012-12-11

    申请号：US12270569

    申请日：2008-11-13

    申请人： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Daniel M. Dreps ,  Edward J. Seminaro

    发明人： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Daniel M. Dreps ,  Edward J. Seminaro

    IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/00 ,  G06F13/42 ,  G06F15/76 ,  G06F9/44 ,  H04L12/28 ,  H04L12/50 ,  H03K19/173 ,  H01L25/00

    CPC分类号： G06F13/385

    摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.

    摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。