公开(公告)号：US07630249B2

公开(公告)日：2009-12-08

申请号：US11766583

申请日：2007-06-21

申请人： Yupin Fong ,  Jun Wan

发明人： Yupin Fong ,  Jun Wan

IPC分类号： G11C11/03

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. For example, after the pulses reach the maximum magnitude the pulse widths are increased. Alternatively, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。 在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。 例如，在脉冲达到最大幅度之后，脉冲宽度增加。 或者，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

公开(公告)号：US07512014B2

公开(公告)日：2009-03-31

申请号：US11316069

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US07508720B2

公开(公告)日：2009-03-24

申请号：US11316475

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US07495956B2

公开(公告)日：2009-02-24

申请号：US12021761

申请日：2008-01-29

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

摘要翻译： 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US20090004843A1

公开(公告)日：2009-01-01

申请号：US11768461

申请日：2007-06-26

申请人： Nima Mokhlesi ,  Jun Wan

发明人： Nima Mokhlesi ,  Jun Wan

IPC分类号： H01L21/768

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

摘要翻译： 公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。 位线在两个分离的金属层的每一个中以4f间距形成，并且布置成在每个层之间交替。 在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

公开(公告)号：US20090003025A1

公开(公告)日：2009-01-01

申请号：US11768468

申请日：2007-06-26

申请人： Nima Mokhlesi ,  Jun Wan

发明人： Nima Mokhlesi ,  Jun Wan

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

摘要翻译： 公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。 在两个分离的金属层的每一个中，位线以4f间距形成，并且布置成在每个层之间交替。 在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

公开(公告)号：US07450435B2

公开(公告)日：2008-11-11

申请号：US11316162

申请日：2005-12-21

申请人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

发明人： Dat Tran ,  Kiran Ponnuru ,  Jian Chen ,  Jeffrey W. Lutze ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

摘要翻译： 根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。 在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。 例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。 如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。 通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。 例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。 这样的字符串可能是有缺陷的，并被映射出存储器件。

公开(公告)号：US20080137424A1

公开(公告)日：2008-06-12

申请号：US12021741

申请日：2008-01-29

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

摘要翻译： 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US07372392B1

公开(公告)日：2008-05-13

申请号：US11679070

申请日：2007-02-26

申请人： Jun Wan ,  Peter R. Holloway

发明人： Jun Wan ,  Peter R. Holloway

IPC分类号： H03M1/12

CPC分类号： H03M1/0607 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45766 ,  H03F2200/264 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45342 ,  H03F2203/45352

摘要： A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal at a first active device switch at the end of the autozero phase having a first voltage polarity and a first magnitude, generating a second voltage pedestal at a second active device switch at the end of the integration phase having an opposite voltage polarity and the first magnitude, and summing the first voltage pedestal with the second voltage pedestal. The difference between the first voltage pedestal and the second voltage pedestal results in a net voltage error. The first and second voltage pedestals have the first magnitude under all operating conditions of the modulator and the two voltage pedestals cancel to yield a small net voltage error.

摘要翻译： 一种用于电流输入ADC中的电荷平衡的方法，包括在积分器输出节点处维持低电容值，其中电容值与积分器输出电压和工作条件无关，在最终的第一有源器件开关处产生第一电压基座 的自相位相具有第一电压极性和第一幅度，在具有相反电压极性和第一幅度的积分相位结束时在第二有源器件开关处产生第二电压基座，并且将第一电压基座与 第二电压基座。 第一电压基座和第二电压基座之间的差异导致净电压误差。 第一和第二电压基座在调制器的所有工作条件下都具有第一幅度，并且两个电压基座取消以产生小的净电压误差。

公开(公告)号：US07331708B2

公开(公告)日：2008-02-19

申请号：US11361912

申请日：2006-02-23

申请人： Eric D. Blom ,  Jun Wan ,  Stuart H. Urie

发明人： Eric D. Blom ,  Jun Wan ,  Stuart H. Urie

IPC分类号： G01K7/14 ,  H03K3/01

CPC分类号： G01K7/01

摘要： A frequency ratio digitizing temperature sensor for generating a linearity-corrected temperature output signal includes an input generation circuit receiving a PTAT current and a CTAT current and a frequency ratio ADC including data and reference oscillators. The input generation circuit generates a first current from the weighted sum of the PTAT current and the CTAT current and also generates a first corrected current being the sum of the first current and a first portion of the PTAT current. The input generation circuit provides a first output current indicative of the PTAT current and a first output voltage generated by applying the first corrected current to a first resistor for use with the data oscillator and provides a second output current being the first corrected current and a second output voltage generated by applying the first current to a second resistor for use with the reference oscillator of the ADC.

摘要翻译： 用于产生线性校正温度输出信号的频率比数字化温度传感器包括接收PTAT电流和CTAT电流的输入产生电路和包括数据和参考振荡器的频率比ADC。 输入产生电路根据PTAT电流和CTAT电流的加权和产生第一电流，并且还产生第一校正电流，该第一校正电流是PTAT电流的第一电流和第一部分之和。 输入产生电路提供指示PTAT电流的第一输出电流和通过将第一校正电流施加到与数据振荡器一起使用的第一电阻器产生的第一输出电压，并提供作为第一校正电流的第二输出电流和第二输出电流 通过将第一电流施加到与ADC的参考振荡器一起使用的第二电阻器产生的输出电压。