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    Forming narrow fins for finFET devices using asymmetrically spaced mandrels
    52.
    发明授权
    Forming narrow fins for finFET devices using asymmetrically spaced mandrels 有权
    使用不对称间隔的心轴形成finFET器件的窄鳍

    公开(公告)号：US08617937B2

    公开(公告)日：2013-12-31

    申请号：US12886850

    申请日：2010-09-21

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

    IPC分类号： H01L21/335

    CPC分类号： H01L29/66795 ,  H01L21/845

    摘要： A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers.

    摘要翻译： 形成鳍状场效应晶体管（finFET）器件的鳍片的方法包括在半导体衬底上形成多个牺牲心轴。 多个牺牲心轴沿着第一方向彼此间隔开第一距离，并且沿第二方向间隔开第二距离。 间隔层形成在牺牲心轴的侧壁上，使得沿着第一方向的牺牲心轴之间的间隔层的部分被合并在一起。 沿着第二方向的牺牲心轴之间的间隔层的部分保持间隔开。 牺牲心轴被去除。 对应于间隔层的图案被转移到半导体层中以形成多个半导体鳍片。 相邻的翅片对在与合并的间隔层相对应的位置处彼此合并。

    Inversion mode varactor
    53.
    发明授权
    Inversion mode varactor 有权
    反转模式变容二极管

    公开(公告)号：US08564040B1

    公开(公告)日：2013-10-22

    申请号：US13570360

    申请日：2012-08-09

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/108

    CPC分类号： H01L29/93 ,  H01L27/1203 ,  H01L29/66174

    摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.

    摘要翻译： 在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物 半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层， 其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

    Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
    55.
    发明授权
    Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance 有权
    极薄的绝缘体上半导体（ETSOI）FET，具有背栅极和降低的寄生电容

    公开(公告)号：US08507989B2

    公开(公告)日：2013-08-13

    申请号：US13108282

    申请日：2011-05-16

    申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66

    CPC分类号： H01L27/1203 ,  H01L21/764 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L2029/42388

    摘要： An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.

    摘要翻译： 在SOI衬底上的非常薄的SOI MOSFET器件在Si衬底上设置有由薄BOX层叠加的背栅层; 在薄BOX层顶部的非常薄的SOI层（ETSOI）; 并且在ETSOI层上的FET器件具有由间隔物绝缘的栅极堆叠。 薄BOX形成在ETSOI通道下面，并在源极和漏极之间提供较厚的电介质，以减少源极/漏极到背栅极寄生电容。 较厚的电介质部分与栅极自对准。 较厚电介质部分内的空隙形成在源/漏区下。 背栅由通过注入损坏的半导体区域确定，并且通过横向蚀刻形成绝缘层并且用电介质反向填充。

    Field Effect Transistor Device with Raised Active Regions
    56.
    发明申请
    Field Effect Transistor Device with Raised Active Regions 失效
    具有有源区域的场效应晶体管器件

    公开(公告)号：US20130071979A1

    公开(公告)日：2013-03-21

    申请号：US13606382

    申请日：2012-09-07

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/336

    CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

    摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

    SOI trench DRAM structure with backside strap
    57.
    发明授权
    SOI trench DRAM structure with backside strap 有权
    具有背面带的SOI沟槽DRAM结构

    公开(公告)号：US08318574B2

    公开(公告)日：2012-11-27

    申请号：US12847208

    申请日：2010-07-30

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

    摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。