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103 条记录 (耗时 0.03 秒)

    Flexible I/O routing resources
    51.
    发明授权
    Flexible I/O routing resources 有权
    灵活的I / O路由资源

    公开(公告)号：US06826741B1

    公开(公告)日：2004-11-30

    申请号：US10289629

    申请日：2002-11-06

    申请人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    发明人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    IPC分类号： G06F1750

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.

    摘要翻译： 在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。 在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由， 可能包括I / O到核心，核到I / O和核心到核心的路由。 在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。 在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。 在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

    Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    53.
    发明授权
    Method and apparatus for performing parallel routing using a multi-threaded routing procedure 有权
    使用多线程路由过程执行并行路由的方法和装置

    公开(公告)号：US08296709B2

    公开(公告)日：2012-10-23

    申请号：US13311996

    申请日：2011-12-06

    申请人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

    发明人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

    摘要翻译： 一种用于设计要在目标设备上实现的系统的方法包括在系统中为网络生成目标设备上的边界框，其中边界框标识可用于路由其相应网络的路由资源。 系统中的网络被分配给要路由的多个线程。 执行线程使得多个网络在其对应的边界框内并行路由。

    Flexible RAM clock enable
    54.
    发明授权
    Flexible RAM clock enable 有权
    灵活的RAM时钟使能

    公开(公告)号：US08271821B2

    公开(公告)日：2012-09-18

    申请号：US12145440

    申请日：2008-06-24

    申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    IPC分类号： G06F1/04 ,  G06F1/12

    CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

    摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

    摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

    Power-aware RAM processing
    58.
    发明授权
    Power-aware RAM processing 有权
    电源感知RAM处理

    公开(公告)号：US07877555B1

    公开(公告)日：2011-01-25

    申请号：US11510018

    申请日：2006-08-24

    申请人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    发明人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    IPC分类号： G06F12/00

    CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

    摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

    摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

    Power-driven timing analysis and placement for programmable logic
    59.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US07861190B1

    公开(公告)日：2010-12-28

    申请号：US10907049

    申请日：2005-03-17

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Periphery clock distribution network for a programmable logic device
    60.
    发明授权
    Periphery clock distribution network for a programmable logic device 有权
    用于可编程逻辑器件的周边时钟分配网络

    公开(公告)号：US07737751B1

    公开(公告)日：2010-06-15

    申请号：US11668521

    申请日：2007-01-30

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    IPC分类号： H03K3/013

    CPC分类号： G06F1/10

    摘要： A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.

    摘要翻译： 可编程逻辑器件（PLD）包括与PLD的高质量，低偏移时钟分配网络分离的信号分配网络，用于从PLD的外围输入/输出区域分配时钟型信号。 信号分配网络包括位于一组外围输入/输出区域附近的中央周边时钟总线，用于将这些区域的时钟信号传导到PLD的时钟脊上。 时钟脊可以专用于信号分配网络，或者可以是覆盖全部或部分PLD的高质量，低偏移时钟分配网络的一部分。 信号分配网络允许比这种高质量的低偏移时钟分配网络更大的偏斜，但是仍然具有比一般的可编程互连和路由资源更高的质量，并且允许较少的偏移。