Systems and methods for multi-stage encoding of concatenated low density parity check codes
    52.
    发明授权
    Systems and methods for multi-stage encoding of concatenated low density parity check codes 有权
    连接低密度奇偶校验码的多级编码的系统和方法

    公开(公告)号:US09048873B2

    公开(公告)日:2015-06-02

    申请号:US13912079

    申请日:2013-06-06

    CPC classification number: H03M13/1171 H03M13/611 H03M13/616

    Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

    Abstract translation: 数据编码系统包括数据编码器电路,其可操作以用低密度奇偶校验码矩阵的分量矩阵对多个数据扇区中的每一个进行编码,并产生输出码字。 数据编码器电路包括可用于计算和组合用于数据扇区的综合征的校正子计算电路。

    Systems and methods for large sector dynamic format insertion
    55.
    发明授权
    Systems and methods for large sector dynamic format insertion 有权
    大型动态格式插入的系统和方法

    公开(公告)号:US08976475B1

    公开(公告)日:2015-03-10

    申请号:US14080946

    申请日:2013-11-15

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one case, a system is disclosed that includes: a data transfer preparation circuit, a transfer characteristic determination circuit, and a a format insertion circuit. The data transfer preparation circuit is operable to receive a user data set and to generate an output data set based upon the user data set; the transfer characteristic determination circuit is operable to determine a distance between a first servo data wedge on a storage medium and a second servo data wedge on the storage medium; and the format insertion circuit is operable to dynamically augment the output data set with formatting information at a location selected based at least in part on the distance between the first servo data wedge and the second servo data wedge.

    Abstract translation: 一般涉及数据处理的系统和方法,更具体地涉及用于分割数据集并恢复分段数据集的系统和方法。 在一种情况下,公开了一种系统,包括:数据传输准备电路,传输特性确定电路和格式插入电路。 数据传输准备电路可操作以接收用户数据集并且基于用户数据集生成输出数据集; 传输特性确定电路可操作以确定存储介质上的第一伺服数据楔与存储介质上的第二伺服数据楔之间的距离; 并且所述格式插入电路可操作以使用至少部分地基于所述第一伺服数据楔和所述第二伺服数据楔之间的距离所选择的位置的格式化信息动态地增大所述输出数据集。

    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling
    60.
    发明申请
    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling 有权
    具有低综合征错误处理的不规则低密度奇偶校验解码器

    公开(公告)号:US20140168811A1

    公开(公告)日:2014-06-19

    申请号:US13777381

    申请日:2013-02-26

    Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.

    Abstract translation: 公开了一种数据处理系统,包括数据解码器电路,错误处理电路和综合检查电路。 数据解码器电路可操作以将数据解码算法应用于解码器输入以产生解码输出,并计算指示解码输出的误差电平的校正子。 错误处理电路可操作以确定解码输出中的任何错误是否涉及用户数据位。 综合征检查器电路可操作以至少部分地基于综合征来触发误差处理电路。

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