公开(公告)号：US07161826B2

公开(公告)日：2007-01-09

申请号：US10879090

申请日：2004-06-30

申请人： Steven Hsu ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Ram Krishnamurthy

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

摘要翻译： 存储器电路包括字线，包括一个或多个存储器单元或子单元的数据存储电路，以及耦合在字线和N个存储单元之间的反相器。 逆变器将输入到单元或子单元的读取端口的字线信号反相。 由于字线逆变器对于每个单元或子单元是局部的，所以DC偏移显着减小，这转化为泄漏电流的减小。

公开(公告)号：US20050219887A1

公开(公告)日：2005-10-06

申请号：US10817941

申请日：2004-04-06

申请人： Steven Hsu ,  Ram Krishnamurthy

发明人： Steven Hsu ,  Ram Krishnamurthy

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/00 ,  G11C15/04

摘要： A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. The two or more cells may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.

摘要翻译： 用于搜索内容可寻址存储器的电路包括产生多个搜索线值的驱动器，其中不同的组合用于实现用于搜索存储器的单热编码方案。 两个或多个单元可以是字的连续位位置，并且可以同步地操作驱动器以产生不同的值组合。

公开(公告)号：US10825509B2

公开(公告)日：2020-11-03

申请号：US16146932

申请日：2018-09-28

申请人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

发明人： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C27/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20190057050A1

公开(公告)日：2019-02-21

申请号：US16160952

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC分类号： G06F13/16 ,  G06F13/28

摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US07250783B2

公开(公告)日：2007-07-31

申请号：US11022800

申请日：2004-12-28

申请人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

发明人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

IPC分类号： G01R31/02

CPC分类号： G11C29/50 ,  G01R31/3012 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

摘要翻译： 电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。 泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

公开(公告)号：US07131055B2

公开(公告)日：2006-10-31

申请号：US10372121

申请日：2003-02-25

申请人： Sanu K. Mathew ,  Ram Krishnamurthy ,  Hoang Q. Dao

发明人： Sanu K. Mathew ,  Ram Krishnamurthy ,  Hoang Q. Dao

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/4107

摘要： A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.

摘要翻译： 维特比解码器包括对每个符号周期执行状态度量更新的ACS单元。 状态度量更新涉及将对应于可能的输入符号的状态量度相加到相应的分支矩阵，比较添加的结果以确定哪个更小，并为下一状态度量选择较小的结果。 ACS单元包括两个并行加法器，其后是并行比较器，其产生多路选择器选择信号。 并行加法器的输出被输入到多路复用器中，并且多路复用器选择信号被输入到多路复用器中用于决定。

公开(公告)号：US07016239B2

公开(公告)日：2006-03-21

申请号：US10676985

申请日：2003-09-30

申请人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Sriram R. Vangal ,  Ram Krishnamurthy

发明人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Sriram R. Vangal ,  Ram Krishnamurthy

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C8/10

摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.

摘要翻译： 寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。 一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。 通过确定数据单元之一的选择来促进智能充电和浮动。

公开(公告)号：US07002375B2

公开(公告)日：2006-02-21

申请号：US10401774

申请日：2003-03-31

申请人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

发明人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

IPC分类号： H03K19/096 ,  H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0963

摘要： A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.

摘要翻译： 基于可变门限强度的过程补偿动态电路和方法提供了一种鲁棒的数字方式来克服制造的模具中存在的固有参数变化。 使用过程补偿动态电路，广泛的鲁棒性和延迟分布变窄，从而提高性能，而不会牺牲最坏情况的鲁棒性。 保持器的强度根据模具泄漏量进行编程。 守门员将具有最佳和最差情况泄漏的最佳强度，从而改善最坏情况下的鲁棒性。

公开(公告)号：US20050225459A1

公开(公告)日：2005-10-13

申请号：US10813084

申请日：2004-03-31

申请人： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

发明人： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehea Ismail

IPC分类号： G06F13/40 ,  H03M5/00

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

摘要翻译： 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US20050122158A1

公开(公告)日：2005-06-09

申请号：US10732791

申请日：2003-12-09

申请人： Atila Alvandpour ,  Ram Krishnamurthy

发明人： Atila Alvandpour ,  Ram Krishnamurthy

IPC分类号： H03K17/16

CPC分类号： H03K17/164

摘要： A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

摘要翻译： 具有经历高到低转换的接收信号的第一反相阈值的静态接收机，以及经历低到高转换的接收信号的第二反相阈值，其中第一反转阈值大于第二反转阈值。 一个实施例包括静态接收器，pFET和nFET，其中当在接收器的输入端口处接收到高电平到低电平的转换时，pFET耦合到输入端口，以有助于提高反转阈值， 并且当在输入端口处接收到低电平到高电平的转换时，nFET耦合到输入端口，以便有助于降低反转阈值。 描述和要求保护其他实施例。