公开(公告)号：US20220100404A1

公开(公告)日：2022-03-31

申请号：US17493988

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christopher Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US20210342090A1

公开(公告)日：2021-11-04

申请号：US16865163

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US10991411B2

公开(公告)日：2021-04-27

申请号：US16104693

申请日：2018-08-17

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Andrea Martinelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation, such as an equalization operation or a dissipation operation, based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. Selecting one of the memory sections for a voltage adjustment operation may also be based on a timer. Equalizing a bias may include biasing a plate line, which may be coupled to a ferroelectric capacitor of a memory cell, to a ground voltage or some non-zero voltage. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US20210012825A1

公开(公告)日：2021-01-14

申请号：US16508772

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/408 ,  G11C11/4091

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US20210011645A1

公开(公告)日：2021-01-14

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.