ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS
    51.
    发明申请
    ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS 有权
    在相变记忆细胞中增强核酸

    公开(公告)号:US20160254050A1

    公开(公告)日:2016-09-01

    申请号:US15154410

    申请日:2016-05-13

    Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

    Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器(PCM)单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中,该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置,其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。

    Techniques for manufacturing a double electrode memory array

    公开(公告)号:US12213325B2

    公开(公告)日:2025-01-28

    申请号:US17499709

    申请日:2021-10-12

    Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.

    ACCESS LINE FORMATION FOR A MEMORY ARRAY

    公开(公告)号:US20250031383A1

    公开(公告)日:2025-01-23

    申请号:US18788475

    申请日:2024-07-30

    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

    MEMORY CELLS FOR STORING OPERATIONAL DATA

    公开(公告)号:US20220172782A1

    公开(公告)日:2022-06-02

    申请号:US17108783

    申请日:2020-12-01

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

    ACCESS LINE FORMATION FOR A MEMORY ARRAY

    公开(公告)号:US20220165795A1

    公开(公告)日:2022-05-26

    申请号:US17671373

    申请日:2022-02-14

    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

    Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells

    公开(公告)号:US11302748B2

    公开(公告)日:2022-04-12

    申请号:US16575743

    申请日:2019-09-19

    Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

    Access line formation for a memory array

    公开(公告)号:US11276731B2

    公开(公告)日:2022-03-15

    申请号:US16534952

    申请日:2019-08-07

    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

    THREE-DIMENSIONAL MEMORY ARRAY
    58.
    发明申请

    公开(公告)号:US20210273015A1

    公开(公告)日:2021-09-02

    申请号:US17320785

    申请日:2021-05-14

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

    Three-dimensional memory array
    60.
    发明授权

    公开(公告)号:US10593730B1

    公开(公告)日:2020-03-17

    申请号:US16156194

    申请日:2018-10-10

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

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