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公开(公告)号：US20160254050A1
公开(公告)日：2016-09-01
申请号：US15154410
申请日：2016-05-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。
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公开(公告)号：US12213325B2
公开(公告)日：2025-01-28
申请号：US17499709
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Gotti , Pavan Reddy K. Aella
Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US20250031383A1
公开(公告)日：2025-01-23
申请号：US18788475
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti
IPC: H10B63/00 , H01L21/3213 , H01L21/768 , H01L23/528 , H10B53/20 , H10N70/00 , H10N70/20
Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
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公开(公告)号：US20220172782A1
公开(公告)日：2022-06-02
申请号：US17108783
申请日：2020-12-01
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.
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公开(公告)号：US20220165795A1
公开(公告)日：2022-05-26
申请号：US17671373
申请日：2022-02-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti
IPC: H01L27/24 , H01L21/3213 , H01L21/768 , H01L45/00 , H01L23/528 , H01L27/11514
Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
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Patent Agency Ranking
公开(公告)号：US11302748B2
公开(公告)日：2022-04-12
申请号：US16575743
申请日：2019-09-19
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Agostino Pirovano , Andrea Redaelli
Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
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公开(公告)号：US11276731B2
公开(公告)日：2022-03-15
申请号：US16534952
申请日：2019-08-07
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti
IPC: H01L27/24 , H01L27/11514 , H01L21/3213 , H01L21/768 , H01L23/528 , H01L45/00
Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
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公开(公告)号：US20210273015A1
公开(公告)日：2021-09-02
申请号：US17320785
申请日：2021-05-14
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Redaelli , Agostino Pirovano
Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
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公开(公告)号：US10923387B2
公开(公告)日：2021-02-16
申请号：US16577012
申请日：2019-09-20
Applicant: Micron Technology, Inc.
Inventor： Marcello Mariani , Anna Maria Conti , Sara Vigano
IPC: H01L27/11551 , H01L21/762 , H01L29/78 , H01L29/744 , H01L21/308 , H01L21/8249 , H01L29/66 , H01L21/8239 , H01L27/102 , H01L29/749 , H01L21/8229 , H01L21/8234 , H01L27/105 , H01L29/423
Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
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公开(公告)号：US10593730B1
公开(公告)日：2020-03-17
申请号：US16156194
申请日：2018-10-10
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Redaelli , Agostino Pirovano
Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
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