公开(公告)号：US11737275B2

公开(公告)日：2023-08-22

申请号：US17233158

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

IPC: H10B43/27 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/50

Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

公开(公告)号：US20230062403A1

公开(公告)日：2023-03-02

申请号：US17508143

申请日：2021-10-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Chet E. Carter ,  Justin D. Shepherdson ,  Collin Howder ,  Joshua Wolanyk

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US20220254810A1

公开(公告)日：2022-08-11

申请号：US17731103

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US20220238444A1

公开(公告)日：2022-07-28

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11348939B2

公开(公告)日：2022-05-31

申请号：US16723136

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US11177269B2

公开(公告)日：2021-11-16

申请号：US16277311

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20210249431A1

公开(公告)日：2021-08-12

申请号：US16787914

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210167082A1

公开(公告)日：2021-06-03

申请号：US16702255

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US10943921B2

公开(公告)日：2021-03-09

申请号：US16751116

申请日：2020-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US10930658B2

公开(公告)日：2021-02-23

申请号：US16449912

申请日：2019-06-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/3213

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.