公开(公告)号：US20220075722A1

公开(公告)日：2022-03-10

申请号：US17527776

申请日：2021-11-16

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C11/16 ,  G11C16/10

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

公开(公告)号：US11182102B2

公开(公告)日：2021-11-23

申请号：US16235168

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US20210103497A1

公开(公告)日：2021-04-08

申请号：US17100622

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

公开(公告)号：US20210064526A1

公开(公告)日：2021-03-04

申请号：US16552246

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz

IPC: G06F12/08 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for remapping data of flash memory indexed by logical block addresses (LBAs) of a host device in response to re-map requests received at a flash memory system from the host device or in response to re-map requests generated at the flash memory system.

公开(公告)号：US10923202B2

公开(公告)日：2021-02-16

申请号：US16054109

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/28 ,  H01L27/115 ,  G11C11/56 ,  G11C16/10

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host performance boost mode of operation to ameliorate erroneous or potentially malicious access to the memory device, and efficiently providing refreshed mapping information to the host during the host performance boost mode of operation.

公开(公告)号：US20200303019A1

公开(公告)日：2020-09-24

申请号：US16894397

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C16/26 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G11C16/32

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.

公开(公告)号：US20200210108A1

公开(公告)日：2020-07-02

申请号：US16293261

申请日：2019-03-05

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include initiating a first plurality of host-requested NAND memory operations of a first type at a first channel of a memory device for a first interval, and, at the completion of the first interval, performing a second plurality of homogeneous, host-requested NAND memory operations of a second type at the first multiple plane memory die for a second interval.

公开(公告)号：US20200043561A1

公开(公告)日：2020-02-06

申请号：US16054109

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/10 ,  G11C11/56 ,  H01L27/115

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host performance boost mode of operation to ameliorate erroneous or potentially malicious access to the memory device, and efficiently providing refreshed mapping information to the host during the host performance boost mode of operation.

公开(公告)号：US12292831B2

公开(公告)日：2025-05-06

申请号：US18616993

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

公开(公告)号：US20250117156A1

公开(公告)日：2025-04-10

申请号：US18774439

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: In accordance with examples as described herein, a memory system may initialize a data optimization operation by transmitting signaling to a host system. For example, the memory system may identify data associated with non-sequential logical block addresses (LBAs), and may indicate the discontinuous LBAs to the host system. In response, the host system may indicate which of the discontinuous LBAs represent sequential data. Accordingly, the memory system may sequentialize the one or more of the discontinuous LBAs to defragment the associated data.