公开(公告)号：US10446197B2

公开(公告)日：2019-10-15

申请号：US15692407

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/10 ,  G11C29/02

摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190122705A1

公开(公告)日：2019-04-25

申请号：US16230251

申请日：2018-12-21

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Reddy Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC分类号： G11C7/10 ,  G11C8/10

摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20160086641A1

公开(公告)日：2016-03-24

申请号：US14954625

申请日：2015-11-30

申请人： Micron Technology, Inc.

发明人： Koji Sakui ,  Peter Sean Feeley

IPC分类号： G11C7/06 ,  G11C7/22

CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C7/106 ,  G11C7/12 ,  G11C7/22 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/108

摘要： Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.

摘要翻译： 一些实施例包括用于在设备的存储器操作期间激活与耦合到不同组的存储器单元的访问线相关联的信号的装置和方法，以及用于在存储器操作的不同时间间隔期间感测设备的数据线以确定值 存储在存储单元中的信息。 每个数据线可以耦合到每组存储器单元的相应存储单元。 在这样的装置和方法中的至少一个中，施加到访问线路的信号可以在存储器操作期间保持激活。

公开(公告)号：US09208833B2

公开(公告)日：2015-12-08

申请号：US13868548

申请日：2013-04-23

申请人： Micron Technology, Inc.

发明人： Koji Sakui ,  Peter Sean Feeley

IPC分类号： G11C16/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C7/106 ,  G11C7/12 ,  G11C7/22 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/108

摘要： Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.

摘要翻译： 一些实施例包括用于在设备的存储器操作期间激活与耦合到不同组的存储器单元的访问线相关联的信号的装置和方法，以及用于在存储器操作的不同时间间隔期间感测设备的数据线以确定值 存储在存储单元中的信息。 每个数据线可以耦合到每组存储器单元的相应存储单元。 在这样的装置和方法中的至少一个中，施加到访问线路的信号可以在存储器操作期间保持激活。

公开(公告)号：US20140119117A1

公开(公告)日：2014-05-01

申请号：US13661498

申请日：2012-10-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Koji Sakui ,  Peter Sean Feeley ,  Akira Goda

IPC分类号： G11C16/04

CPC分类号： H01L23/528 ,  G11C11/5671 ,  G11C16/0483 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/535 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4975 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

摘要翻译： 公开了装置和方法，包括具有耦合到公共源的存储器单元的垂直串行的装置和与每行垂直串相关联的多个数据线的装置。 与行相关联的每个数据行被耦合到行中的至少一个垂直字符串。 描述附加的装置和方法。