公开(公告)号：US20150074370A1

公开(公告)日：2015-03-12

申请号：US14542750

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/06 ,  G06F12/0653 ,  Y02D10/13

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

Abstract translation: 描述访问存储器单元的方法，分配存储器请求的方法，系统和存储器控制器。 在一种这样的方法中，其中存储器单元被划分为存储器单元的至少第一区域和存储器单元的第二区域，根据第一地址定义访问第一区域中的存储器单元，并且访问第二区域中的存储器单元 根据与第一地址定义不同的第二地址定义。 描述其他实施例。

公开(公告)号：US08838899B2

公开(公告)日：2014-09-16

申请号：US13960634

申请日：2013-08-06

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F13/28 ,  G11C19/00 ,  G06F9/38 ,  G06F15/78

CPC classification number: G11C19/00 ,  G06F9/3877 ,  G06F15/7821 ,  G06F15/785 ,  Y02D10/12 ,  Y02D10/13

Abstract: One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a compute engine which performs operations on operands retrieved from the buffer, and stores results of the operations to the buffer. Such a compute engine buffer includes a compute buffer having storage units which may be electrically connected or isolated, based on the size of the operands to be stored and the configuration of the compute engine. The compute engine buffer further includes a data buffer, which may be a simple buffer. Operands may be copied to the data buffer before being copied to the compute buffer, which may save additional clock cycles for the compute engine, further increasing the compute engine efficiency.

Abstract translation: 一种或多种本技术提供了一种配置成操纵数据并提高计算引擎效率的计算引擎缓冲器。 一个这样的计算引擎缓冲器连接到计算引擎，该计算引擎对从缓冲器检索的操作数执行操作，并将操作的结果存储到缓冲器。 这样的计算引擎缓冲器包括基于要存储的操作数的大小和计算引擎的配置的具有可以电连接或隔离的存储单元的计算缓冲器。 计算引擎缓冲器还包括数据缓冲器，其可以是简单缓冲器。 在复制到计算缓冲区之前，操作数可以复制到数据缓冲区，这可能为计算引擎节省额外的时钟周期，进一步提高了计算引擎的效率。

公开(公告)号：US11928055B2

公开(公告)日：2024-03-12

申请号：US17975164

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/02 ,  H04W4/029 ,  H04W4/33 ,  G06F9/30 ,  H04B17/24 ,  H04L101/622 ,  H04L101/69 ,  H04W84/12

CPC classification number: G06F12/0607 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/026 ,  H04W4/029 ,  H04W4/33 ,  G06F9/30134 ,  H04B17/24 ,  H04L2101/622 ,  H04L2101/69 ,  H04W84/12

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20230195659A1

公开(公告)日：2023-06-22

申请号：US17559320

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Robert Walker ,  Laurent Isenegger

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F13/1642 ,  G06F13/1621 ,  G06F13/4221 ,  G06F9/30101

Abstract: Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US20220019536A1

公开(公告)日：2022-01-20

申请号：US16928766

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Ashay Narsale ,  Robert Walker

IPC: G06F12/0862 ,  G06F13/16 ,  G06F13/42

Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.

公开(公告)号：US20210223999A1

公开(公告)日：2021-07-22

申请号：US17223684

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US10970247B2

公开(公告)日：2021-04-06

申请号：US16545907

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F9/30 ,  G06F15/78 ,  G06F9/38

Abstract: An internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.

公开(公告)号：US20210042219A1

公开(公告)日：2021-02-11

申请号：US17079138

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

公开(公告)号：US20200272562A1

公开(公告)日：2020-08-27

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20200264804A1

公开(公告)日：2020-08-20

申请号：US16280607

申请日：2019-02-20

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.