公开(公告)号：US11294848B1

公开(公告)日：2022-04-05

申请号：US17075153

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer

IPC: G06F13/42 ,  G06F13/20 ,  H01L23/538

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

公开(公告)号：US20220070108A1

公开(公告)日：2022-03-03

申请号：US17007701

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  David Patrick

IPC: H04L12/801 ,  H04L29/12 ,  H04L12/879

Abstract: A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

公开(公告)号：US20220070096A1

公开(公告)日：2022-03-03

申请号：US17007354

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: H04L12/741 ,  H04L12/725

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers by using a single field to encode multiple elements. Instead of including separate fields for each element, one or more encoded fields may be used, each of which is decoded to determine two or more values for the data packet. A receiving device decodes the encoded data field to retrieve the two or more values.

公开(公告)号：US20220068324A1

公开(公告)日：2022-03-03

申请号：US17007876

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer

IPC: G11C7/10 ,  G06F9/30 ,  G06F13/16 ,  H01L23/538

Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

公开(公告)号：US20220066969A1

公开(公告)日：2022-03-03

申请号：US17007592

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： David Patrick ,  Tony Brewer

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H04L12/741

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

公开(公告)号：US10606693B2

公开(公告)日：2020-03-31

申请号：US15856910

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Bryan Hornung ,  Tony Brewer

IPC: G06F11/00 ,  G06F11/10

Abstract: Devices and techniques for memory controller implemented error correction code (ECC) memory are disclosed herein. ECC groups may be placed across banks of the memory. In some examples, an ECC group is a collection of bytes equal to one row in one bank. Also, the placement may restrict a given bank to a single member of the ECC group. A memory operation can be received and executed using the ECC groups.

公开(公告)号：US12236120B2

公开(公告)日：2025-02-25

申请号：US17870254

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.

公开(公告)号：US20250030635A1

公开(公告)日：2025-01-23

申请号：US18908196

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: H04L45/745 ,  H04L45/302

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers by using a single field to encode multiple elements. Instead of including separate fields for each element, one or more encoded fields may be used, each of which is decoded to determine two or more values for the data packet. A receiving device decodes the encoded data field to retrieve the two or more values.

公开(公告)号：US20240311149A1

公开(公告)日：2024-09-19

申请号：US18669104

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/78

CPC classification number: G06F9/3004 ,  G06F9/325 ,  G06F9/466 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/781

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

公开(公告)号：US20240232111A1

公开(公告)日：2024-07-11

申请号：US18610905

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F13/364 ,  G06F30/3953

CPC classification number: G06F13/364 ,  G06F30/3953

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.