公开(公告)号：US20240370185A1

公开(公告)日：2024-11-07

申请号：US18774803

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US12001279B2

公开(公告)日：2024-06-04

申请号：US18048284

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC classification number: G06F11/1004 ,  H03M13/095 ,  H03M13/611 ,  G06F11/1008

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

公开(公告)号：US20240134740A1

公开(公告)日：2024-04-25

申请号：US18048284

申请日：2022-10-19

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: H03M13/09 ,  H03M13/00

CPC classification number: H03M13/095 ,  H03M13/611

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

公开(公告)号：US20240028244A1

公开(公告)日：2024-01-25

申请号：US17873046

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Nicola Pantaleo ,  Leonid Minz

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0679 ,  G06F3/0611

Abstract: Methods of operating memory systems with input/output expanders for multi-channel status reads (and associated systems and devices) are disclosed herein. In one embodiment, a method comprises receiving, via a controller-side communication channel, a multi-channel status read command at a first interface of an input/output expander. The method further comprises, based at least in part on receiving the multi-channel status read command, (a) transmitting, via a second interface of the input/output expander, a status read command to logical units over each of two or more memory-side channels; (b) receiving, at the second interface, status read data from the logical units over each memory-side channel of the two or more memory-side channels; and (c) transmitting, via the first interface, the status read data onto the controller-side communication channel.

公开(公告)号：US11860714B1

公开(公告)日：2024-01-02

申请号：US18048286

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Chandrakanth Rapalli ,  Tal Sharifie

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0766 ,  G06F11/1096

Abstract: Methods, systems, and devices for error notification using an external channel are described. In some cases, a memory system having a host-driven logical block interface may issue a notification of a detected error using an out of band channel. For example, after receiving a data unit from a host system but prior to storing the data in a memory array of the memory system, the memory system may transmit an acknowledgment to host system to indicate that the data was successfully received. As part of storing the data, the memory system may transfer the data along data paths between various components and perform parity checks at each component. If the memory system detects an error along a data path, the memory system may issue a notification of the error to the host system over the out of band channel.

公开(公告)号：US20230290426A1

公开(公告)日：2023-09-14

申请号：US17692262

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: G11C29/50

CPC classification number: G11C29/50004

Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

公开(公告)号：US20230289307A1

公开(公告)日：2023-09-14

申请号：US18119578

申请日：2023-03-09

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

CPC classification number: G06F13/30 ,  G06F13/1668

Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

公开(公告)号：US11675709B2

公开(公告)日：2023-06-13

申请号：US17494740

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/657

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US11669456B2

公开(公告)日：2023-06-06

申请号：US17452764

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Yoav Weinberg

IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0891

CPC classification number: G06F12/0882 ,  G06F9/30047 ,  G06F9/30101 ,  G06F12/0828 ,  G06F12/0891

Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.

公开(公告)号：US20220294473A1

公开(公告)日：2022-09-15

申请号：US17831357

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  G06F11/10

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.