摘要:
It is an object of the present invention to provide a ferrite carrier core material and a ferrite carrier for an electrophotographic developer, which have an excellent charging property, hardly cause carrier scattering due to cracking and chipping of the core material, and have a prolonged life, and methods for manufacturing these, and an electrophotographic developer using the ferrite carrier. For this object, the ferrite carrier core material and a ferrite carrier for an electrophotographic developer, wherein (1) the ferrite composition contains 0.5 to 2.5% by weight of Sr, and the presence amount of Sr—Fe oxides satisfies a specific conditional expression, (2) the distribution in the number of the shape factor SF-2 is in a specific range, (3) the BET specific surface area is 0.15 to 0.30 m2/g, (4) the average particle diameter D50 is 20 to 35 μm, and (5) the magnetization is 50 to 65 Am2/kg.
摘要:
Employment of a carrier core material for an electrophotographic developer containing 0.8 to 5% by weight of Mg, 0.1 to 1.5% by weight of Ti, 60 to 70% by weight of Fe and 0.2 to 2.5% by weight of Sr and having an amount of Sr dissolved with a pH4 standard solution of 80 to 1000 ppm, a carrier using the core material and a process for producing them, and an electrophotographic developer using the carrier.
摘要:
There is provided a ferrite core material for an electrophotographic developer, the ferrite core material having a ferrite particle composition represented by the formula (1) shown below, containing SrO replacing a part of (MnO) and/or (MgO) in the formula (1) shown below, and having a Cl concentration of 0.1 to 100 ppm, as measured by an elution method of the ferrite core material: (MnO)x(MgO)y(Fe2O3)z (1) wherein x=35 to 45 mol %, y=5 to 15 mol %, z=40 to 60 mol %, and x+y+z=100 mol %.
摘要翻译:提供一种用于电子照相显影剂的铁氧体芯材料,该铁氧体磁芯材料具有如下所示的式(1)所示的铁氧体颗粒组合物,其含有SrO,其代替式(1)中的(MnO)和/或(MgO)的一部分, 1),并且通过铁氧体磁心材料:(MnO)x(MgO)y(Fe 2 O 3)z(1)的洗脱方法测定的Cl浓度为0.1〜100ppm,其中x = 35〜45mol %,y = 5〜15摩尔%,z = 40〜60摩尔%,x + y + z = 100摩尔%。
摘要:
A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.
摘要:
A centrifugal fan has a circular main plate driven and rotated by a motor rotary shaft, a plurality of blades fixed to an outer circumferential portion of the main plate and spaced apart at predetermined intervals in a circumferential direction of the main plate, and a side plate attached to ends of the blades opposite to the main plate. An air inlet port is formed at the center of the side plate. The side plate inclines outward in centrifugal directions from the air inlet port and has an arcuate cross section with a predetermined radius of curvature. A dead water region reducing space is formed between the blades and the side plate. The dead water region reducing space forms a smooth flow between the two surfaces of each blade, bringing about desirable blade performance.
摘要:
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要:
It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.
摘要:
The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.
摘要:
First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.
摘要:
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.