公开(公告)号：US08716081B2

公开(公告)日：2014-05-06

申请号：US11686475

申请日：2007-03-15

申请人： Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

发明人： Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

IPC分类号： H01L29/76

CPC分类号： H01L29/94 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/11

摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.

摘要翻译： 用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。 示例设备包括以下。 形成为围绕衬底上的有源区域的隔离膜。 形成在有源区域的一部分上的栅极电介质和栅电极。 与栅电极相邻的衬底中的源极元件和漏极元件。 漏极元件由漏区和底板区组成。 漏极区域位于底板区域和栅极结构之间。 电容器电介质和电容器顶板在底板区域的至少部分上方。

公开(公告)号：US07541234B2

公开(公告)日：2009-06-02

申请号：US11266024

申请日：2005-11-03

申请人： Chong Kwang Chang ,  Haoren Zhuang ,  Matthias Lipinski ,  Shailendra Mishra ,  O Sung Kwon ,  Tjin Tjin Tjoa ,  Young Gun Ko

发明人： Chong Kwang Chang ,  Haoren Zhuang ,  Matthias Lipinski ,  Shailendra Mishra ,  O Sung Kwon ,  Tjin Tjin Tjoa ,  Young Gun Ko

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

摘要翻译： 集成电路晶体管可以通过在集成电路基板的第一有源区域和集成电路基板的第二有源区域上的含碳层同时去除光致抗蚀剂层来制造，以在第二层上露出氮化物应力产生层 活动区域。 可以使用单个掩模来限定用于去除第一有源区域上的光致抗蚀剂层的第二有源区域和用于将源极/漏极区域注入到第二有源区域中。

公开(公告)号：US10901882B1

公开(公告)日：2021-01-26

申请号：US16881891

申请日：2020-05-22

申请人： Saibalesh Mukhopadhyay ,  Shailendra Mishra

发明人： Saibalesh Mukhopadhyay ,  Shailendra Mishra

IPC分类号： G06F11/36 ,  G06F11/30 ,  G06F11/34

摘要： Systems and methods are disclosed that determine a duration and resources for testing software. In some implementations, the system performs operations including determining functions performed by applications of the software product, and determining categories based on the functions, the categories including a lowest-criticality category and a highest-criticality category. The operations also include determining degrees of change to the applications and test scripts corresponding to the degrees of change. The operations also include generating a data structure based on the categories and the degrees of change, the data structure including columns identifying the categories in an order from lowest to highest criticality. The operations also include determining weights corresponding to distances of the categories from the highest-criticality category. The operations also include determining a set of test scripts based on the weights, the test scripts, and the degree of change indicators, and determining the resources based on the set of test scripts.

公开(公告)号：US08178417B2

公开(公告)日：2012-05-15

申请号：US12107751

申请日：2008-04-22

申请人： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

发明人： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

摘要翻译： 公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。 通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。 第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

公开(公告)号：US20080157223A1

公开(公告)日：2008-07-03

申请号：US11617552

申请日：2006-12-28

申请人： Lee Wee Teo ,  Yong Meng Lee ,  Jeffrey Chee ,  Shyue Seng Tan ,  Chung Woh Lai ,  Johnny Widodo ,  Zhao Lun ,  Shailendra Mishra

发明人： Lee Wee Teo ,  Yong Meng Lee ,  Jeffrey Chee ,  Shyue Seng Tan ,  Chung Woh Lai ,  Johnny Widodo ,  Zhao Lun ,  Shailendra Mishra

IPC分类号： H01L27/088 ,  H01L21/77 ,  G06F17/50

CPC分类号： H01L21/823807 ,  G06F17/5063 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/7843

摘要： A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.

摘要翻译： 提供了一种用于制造具有多个MOSFET器件的集成电路的方法，包括以下步骤：提供多个MOSFET器件，每个MOSFET器件具有与其相关联的第一和第二结构参数，其中第一和第二 选择每个设备的结构参数以提供设备的性能参数的值基本上等于预定参考值，所述预定参考值对于每个设备是相同的。

公开(公告)号：US20080150074A1

公开(公告)日：2008-06-26

申请号：US11614961

申请日：2006-12-21

申请人： Shailendra Mishra ,  Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Johnny Widodo

发明人： Shailendra Mishra ,  Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Johnny Widodo

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L21/76283 ,  H01L21/823481

摘要： An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

摘要翻译： 提供一种集成电路系统，包括提供衬底，在衬底中形成隔离结构基底而不去除衬底，以及在隔离结构基底旁边的衬底中形成第一晶体管。

公开(公告)号：US20070099126A1

公开(公告)日：2007-05-03

申请号：US11266024

申请日：2005-11-03

申请人： Chong Chang ,  Haoren Zhuang ,  Matthias Lipinski ,  Shailendra Mishra ,  O Kwon ,  Tjin Tjoa ,  Young Ko

发明人： Chong Chang ,  Haoren Zhuang ,  Matthias Lipinski ,  Shailendra Mishra ,  O Kwon ,  Tjin Tjoa ,  Young Ko

IPC分类号： G03F7/26

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

摘要翻译： 集成电路晶体管可以通过在集成电路基板的第一有源区域和集成电路基板的第二有源区域上的含碳层同时去除光致抗蚀剂层来制造，以在第二层上露出氮化物应力产生层 活动区域。 可以使用单个掩模来限定用于去除第一有源区域上的光致抗蚀剂层的第二有源区域和用于将源极/漏极区域注入到第二有源区域中。

公开(公告)号：US20210365356A1

公开(公告)日：2021-11-25

申请号：US17151288

申请日：2021-01-18

申请人： Saibalesh Mukhopadhyay ,  Shailendra Mishra

发明人： Saibalesh Mukhopadhyay ,  Shailendra Mishra

IPC分类号： G06F11/36 ,  G06F11/30 ,  G06F11/34

摘要： Systems and methods are disclosed that determine a duration and resources for testing software. In some implementations, the system performs operations including determining functions performed by applications of the software product, and determining categories based on the functions, the categories including a lowest-criticality category and a highest-criticality category. The operations also include determining degrees of change to the applications and test scripts corresponding to the degrees of change. The operations also include generating a data structure based on the categories and the degrees of change, the data structure including columns identifying the categories in an order from lowest to highest criticality. The operations also include determining weights corresponding to distances of the categories from the highest-criticality category. The operations also include determining a set of test scripts based on the weights, the test scripts, and the degree of change indicators, and determining the resources based on the set of test scripts.

公开(公告)号：US08676841B2

公开(公告)日：2014-03-18

申请号：US12548290

申请日：2009-08-26

申请人： Anand Srinivasan ,  Rakesh Komuravelli ,  Shailendra Mishra

发明人： Anand Srinivasan ,  Rakesh Komuravelli ,  Shailendra Mishra

IPC分类号： G06F17/30 ,  G06F9/30

CPC分类号： G06K9/62

摘要： Techniques for detecting recurring non-occurrences of an event. In one embodiment, techniques are provided for detecting the non-occurrence of an event within each of a series of time periods following the occurrence of another event. Language extensions are provided that enable queries to be formulated for detecting recurring non-occurrence of an event following occurrence of a triggering event.

摘要翻译： 检测事件的重复出现的技术。 在一个实施例中，提供了用于检测在发生另一事件之后的一系列时间段内的每个事件中不发生事件的技术。 提供了语言扩展，使查询能够被制定成用于检测触发事件发生后的事件的循环不发生。

公开(公告)号：US08138053B2

公开(公告)日：2012-03-20

申请号：US11763561

申请日：2007-06-15

申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。