公开(公告)号：US07836290B2

公开(公告)日：2010-11-16

申请号：US11363625

申请日：2006-02-28

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/44

CPC分类号： G06F9/3806 ,  G06F9/3863 ,  G06F9/3867

摘要： A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.

摘要翻译： 一种技术恢复返回地址堆栈（RAS）内容，并恢复RAS堆栈顶部（TOS）指针的对齐，用于由于推测操作，无序指令处理和异常处理引起的错误预测。 在本发明的至少一个实施例中，一种装置包括推测执行处理器流水线，用于在流水线的第一阶段保持相对于指令流的返回地址的第一结构，用于维持相对于指令流的返回地址的至少第二结构 在管道的第二阶段。 管道的第二阶段比第一阶段管道更深。 该装置包括可操作以至少将从第二结构返回地址再现到第一结构的电路。

公开(公告)号：US07689813B2

公开(公告)日：2010-03-30

申请号：US11083263

申请日：2005-03-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857

摘要： Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued.

摘要翻译： 本发明的实施例提供了一种便于在执行前处理器中执行存储器屏障（membar）指令的系统，其中，在允许执行后续指令之前，该指令强制缓冲的负载和存储完成。

公开(公告)号：US07650487B2

公开(公告)日：2010-01-19

申请号：US11371143

申请日：2006-03-08

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Sherman H. Yip

IPC分类号： G06F9/44

CPC分类号： G06F9/30087 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/3017 ,  G06F9/3838 ,  G06F9/3857

摘要： A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.

摘要翻译： 用于协调处理器中允许指令执行无序的指令的执行的技术包括解码根据处理器的指令集定义的特定指令。 然后将对应于特定指令的辅助指令序列引入到可执行操作流中。 相应的助手序列包括第一人造依赖指令，其对与实际不用作特定指令执行的操作的寄存器源或目标的寄存器进行编码依赖关系。

公开(公告)号：US07647477B2

公开(公告)日：2010-01-12

申请号：US10996027

申请日：2004-11-23

申请人： Paul Caprioli ,  Shailender Chaudhry

发明人： Paul Caprioli ,  Shailender Chaudhry

IPC分类号： G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/382 ,  G06F9/3844 ,  G06F9/3846

摘要： Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch instruction group includes a branch type instruction, a branch target is characterized in relation to a fetch boundary, which delimits a memory region contiguous with the memory region that hosts the currently fetched instruction group. Instruction prefetching is included based, at least in part, on the predecoded characterization of the branch target.

摘要翻译： 检查当前获取的指令组并确定当前获取的指令组的分支行为，允许智能指令预取。 当前获取的指令组被预解码，并且假设当前获取指令组包括分支类型指令，则分支目标与获取边界相关，其限定与承载当前获取的指令组的存储器区域相邻的存储器区域 。 基于至少部分地基于分支目标的预解码特征来包括指令预取。

公开(公告)号：US07590830B2

公开(公告)日：2009-09-15

申请号：US11068626

申请日：2005-02-28

申请人： Shailender Chaudhry ,  Paul Caprioli

发明人： Shailender Chaudhry ,  Paul Caprioli

IPC分类号： G06F9/00 ,  G06F9/26

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the instruction flow for a high bandwidth pipeline utilized in advanced performance environments. Branch predictions are concurrently generated for multiple branch-type instructions. The concurrently generated branch predictions are then supplied for further processing of the corresponding branch-type instructions.

摘要翻译： 同时分支预测多种分支式指令对高性能环境的要求。 多分支式指令的并行预测为高级性能环境中使用的高带宽管道提供了指令流程。 对于多个分支类型的指令同时生成分支预测。 然后提供同时产生的分支预测用于进一步处理对应的分支型指令。

公开(公告)号：US07472264B2

公开(公告)日：2008-12-30

申请号：US11479890

申请日：2006-06-30

申请人： Edmond H. Yip ,  Paul Caprioli ,  Shailender Chaudhry ,  Jiejun Lu

发明人： Edmond H. Yip ,  Paul Caprioli ,  Shailender Chaudhry ,  Jiejun Lu

IPC分类号： G06F9/42

CPC分类号： G06F9/3844 ,  G06F9/30054 ,  G06F9/3806

摘要： One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and uses state information that is specific to the process to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.

摘要翻译： 本发明的一个实施例提供一种预测跳转指令的跳转目标的系统。 在运行过程中，系统在执行进程时开始获取跳转指令。 接下来，系统使用用于该过程的程序计数器，并且使用特定于处理的状态信息来查找跳转指令的跳转目标。 最后，系统使用查找返回的跳转目标作为跳转指令的预测跳转目标。

公开(公告)号：US20080172549A1

公开(公告)日：2008-07-17

申请号：US11654271

申请日：2007-01-16

申请人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

发明人： Paul Caprioli ,  Shailender Chaudhry ,  Sherman H. Yip

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30181 ,  G06F9/30189 ,  G06F11/3612

摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.

摘要翻译： 本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。 在运行期间，系统对通常在正常执行模式下执行的指令进行计数。 接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。 在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。

公开(公告)号：US07293161B1

公开(公告)日：2007-11-06

申请号：US11106180

申请日：2005-04-13

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/48

CPC分类号： G06F9/383 ,  G06F9/30181 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3863 ,  G06F12/0862

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。 在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。 如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。

公开(公告)号：US07293160B2

公开(公告)日：2007-11-06

申请号：US11058521

申请日：2005-02-14

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order, wherein issuing the instructions involves decoding the instructions. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue. Simultaneously, the processor feeds instructions from a deferred SRAM into the decode unit, and these instructions eventually pass into the deferred queue. In this way, at the start of deferred mode, deferred instructions can issue from the deferred queue without having to pass through the decode unit, thereby providing time for deferred instructions from the deferred SRAM to progress through a decode unit in order to read input values for the decoded instruction, but not to be re-decoded.

摘要翻译： 本发明的一个实施例提供了一种在支持推测执行的处理器中重新发布延迟指令时有助于消除重新启动损失的系统。 在正常执行模式期间，系统以程序顺序发出执行指令，其中发出指令涉及解码指令。 在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非延迟 指令以程序顺序执行。 当在执行提前模式下解决未解决的数据依赖关系时，处理器开始以延迟模式执行延迟指令。 在这样做时，处理器最初从延迟队列中发出已被解码的延迟指令。 同时，处理器将来自延迟SRAM的指令送入解码单元，并且这些指令最终进入延迟队列。 以这种方式，在延迟模式开始时，延迟指令可以从延迟队列中发出，而不必通过解码单元，从而为延迟的SRAM提供延迟指令的时间，以进行解码单元以便读取输入值 对于解码的指令，但不被重新解码。

公开(公告)号：US07263603B2

公开(公告)日：2007-08-28

申请号：US10923219

申请日：2004-08-20

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instructions in a speculative-execution mode. The system also maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.

摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免写后读取（RAW）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到停顿状态时，系统生成检查点，并以推测执行模式执行指令和后续指令。 该系统还维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 系统使用这种依赖信息来避免在推测执行模式下的RAW危害。